參數(shù)資料
型號： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 94/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標準包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 85 OF 109
09/25/03 Revision 1.09
14.1.34
UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS
REGISTER – OFFSET 58h
Bit
Function
Type
Description
31:0
Upstream
Memory Limit
Address
R/W
Defines bits [63:32] of the upstream memory limit
Reset to 0
14.1.35
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Posted Write
Parity Error
R/W
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer any read data from the target after 224 attempts.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set.
1: P_SERR# is not assert if this event occurs.
Reset to 0
2
Posted Write
Non-Delivery
R/W
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 224 attempts.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
3
Target Abort
During Posted
Write
R/W
Controls PI7C7300A’s ability to assert P_SERR# when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
4
Master Abort On
Posted Write
R/W
Controls PI7C7300A’s ability to assert P_SERR# when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
5
Delayed Write
Non-Delivery
R/W
Controls PI7C7300A’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 224 attempts.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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