參數(shù)資料
| 型號： | PI7C7300ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 17/109頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 產品變化通告： | Product Discontinuation 09/Dec/2010 |
| 標準包裝： | 40 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應商設備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 15 OF 109
09/25/03 Revision 1.09
Name
Pin #
Type
Description
P_M66EN
V18
PI
Primary Interface 66MHz Operation.
This input is used to specify if PI7C7300A is capable
of running at 66MHz. For 66MHz operation on the
Primary bus, this signal should be pulled “HIGH”. For
33MHz operation on the Primary bus, this signal
should be pulled “LOW”.
In this condition,
S1_M66EN and S2_M66EN will both need to be
“LOW”, forcing both secondary buses to run at 33MHz
also.
3.3
SECONDARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
S1_AD[31:0],
S2_AD[31:0]
B20, B19, C20,
C19, C18, D20,
D19, D17, E19,
E18, E17, F20,
F19, F17, G20,
G19, L20, L19,
L18, M20, M19,
M17, N20, N19,
N18, N17, P17,
R20, R19, R18,
T20, T19
J4, H1, H2, H3,
H4, G1, G3, G4,
F2, F3, F4, E1, E4,
D1, C1, B1, C5,
B5, D6, C6, B6,
A6, C7, B7, D8,
C8, D9, C9, B9,
A9, D10, C10
PB
Secondary Address/Data. Multiplexed address and
data bus. Address is indicated by S1_FRAME# or
S2_FRAME# assertion. Write data is stable and valid
when S1_IRDY# or S2_IRDY# is asserted and read
data is stable and valid when S1_IRDY# or S2_IRDY#
is asserted. Data is transferred on rising clock edges
when both S1_IRDY# or S2_IRDY# and S1_TRDY#
or S2_TRDY# are asserted. During bus idle,
PI7C7300A drives S1_AD or S2_AD to a valid logic
level when S1_GNT# or S2_GNT# is asserted
respectively.
S1_CBE[3:0],
S2_CBE[3:0]
E20, G18, K17,
P20
F1, A1, A4, A7
PB
Secondary Command/Byte Enables. Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C7300A drives
S1_CBE[3:0] or S2_CBE[3:0] to a valid logic level
when the internal grant is asserted.
S1_PAR,
S2_PAR
K18,
B4
PB
Secondary Parity. Parity is even across S1_AD[31:0],
S1_CBE[3:0], and S1_PAR or S2_AD[31:0],
S2_CBE[3:0], and S2_PAR (i.e. an even number of
1’s). S1_PAR or S2_PAR is an input and is valid and
stable one cycle after the address phase (indicated by
assertion of S1_FRAME# or S2_FRAME#) for address
parity. For write data phases, S1_PAR or S2_PAR is
an input and is valid one clock after S1_IRDY#
S2_IRDY# is asserted. For read data phase, S1_PAR
or S2_PAR is an output and is valid one clock after
S1_TRDY# or S2_TRDY# is asserted. Signal S1_PAR
or S2_PAR is tri-stated one cycle after the S1_AD or
S2_AD lines are tri-stated. During bus idle,
PI7C7300A drives S1_PAR or S2_PAR to a valid logic
level when the internal grant is asserted.
S1_FRAME#,
S2_FRAME#
H20,
D2
PSTS
Secondary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of
S1_FRAME# or S2_FRAME# indicates the final data
phase requested by the initiator. Before being tri-
stated, it is driven to a de-asserted state for one cycle.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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