參數(shù)資料
型號(hào)： PI7C7300ANAE
廠商： Pericom
文件頁(yè)數(shù)： 67/109頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 60 OF 109
09/25/03 Revision 1.09
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
02 (asserted)
Posted Write
Downstream
Secondary
1 / 1
03
Posted Write
Upstream
Primary
1 / 1
1
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
7.4
SYSTEM ERROR (SERR#) REPORTING
PI7C7300A uses the P_SERR# signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section
7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the
following conditions apply:
!
For PI7C7300A to assert P_SERR# for any reason, the SERR# enable bit must be
set in the command register.
!
Whenever PI7C7300A asserts P_SERR#, PI7C7300A must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300A
asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and
the SERR# forward enable bit is set in the bridge control register. In addition,
PI7C7300A also sets the received system error bit in the secondary status register.
PI7C7300A also conditionally asserts P_SERR# for any of the following reasons:
!
Target abort detected during posted write transaction
!
Master abort detected during posted write transaction
!
Posted write data discarded after 224 (default) attempts to deliver (224 target retries
received)
!
Parity error reported on target bus during posted write transaction (see previous
section)
!
Delayed write data discarded after 224 (default) attempts to deliver (224 target retries
received)
!
Delayed read data cannot be transferred from target after 224 (default) attempts (224
target retries received)
相關(guān)PDF資料
PDF描述
PI7C7300DNAE IC PCI-PCI BRIDGE 3PORT 272-BGA
PI7C8140AMAE IC PCI-PCI BRIDGE 2PORT 128-QFP
PI7C8150ANDE IC PCI-PCI BRIDGE 2PORT 256-PBGA
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開(kāi)發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*