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參數(shù)資料
| 型號(hào)： | PI7C7300ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 32/109頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2010 |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 29 OF 109
09/25/03 Revision 1.09
If PI7C7300A is unable to obtain read data from the target after 224 (default) or 232
(maximum) attempts, PI7C7300A will report a system error. The number of attempts is
programmable. PI7C7300A also asserts P_SERR# if the primary SERR# enable bit is set
in the command register. See Section 7.4 for information on the assertion of P_SERR#.
Once PI7C7300A receives DEVSEL# and TRDY# from the target, it transfers the data
read to the opposite direction read data queue, pointing toward the opposite inter-face,
before terminating the transaction. For example, read data in response to a downstream
read transaction initiated on the primary bus is placed in the upstream read data queue.
The PI7C7300A can accept one DWORD of read data each PCI clock cycle; that is, no
master wait states are inserted. The number of DWORD transferred during a delayed
read transaction depends on the conditions given in Table 4-5 (assuming no disconnect is
received from the target).
4.7.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is
at the head of the read data queue, and all ordering constraints with posted write
transactions have been satisfied, the PI7C7300A transfers the data to the initiator when
the initiator repeats the transaction. For memory read transactions, PI7C7300A aliases
the memory read, memory read line, and memory read multiple bus commands when
matching the bus command of the transaction to the bus command in the delayed
transaction queue. PI7C7300A returns a target disconnect along with the transfer of the
last DWORD of read data to the initiator. If PI7C7300A initiator terminates the
transaction before all read data has been transferred, the remaining read data left in data
buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read data
from data buffers while the read transaction on the target bus is still in progress and
before a read boundary is reached on the target bus, the read transaction starts operating
in flow-through mode. Because data is flowing through the data buffers from the target to
the initiator, long read bursts can then be sustained. In this case, the read transaction is
allowed to continue until the initiator terminates the trans-action, or until an aligned 4KB
address boundary is reached, or until the buffer fills, whichever comes first. When the
buffer empties, PI7C7300A reflects the stalled condition to the initiator by disconnecting
the initiator with data. The initiator may retry the transaction later if data are needed. If
the initiator does not need any more data, the initiator will not continue the disconnected
transaction. In this case, PI7C7300A will start the master timeout timer. The remaining
read data will be discarded after the master timeout timer expires. To provide better
latency, if there are any other pending data for other transactions in the RDB (Read Data
Buffer), the remaining read data will be discarded even though the master timeout timer
has not expired.
PI7C7300A implements a master timeout timer that starts counting when the delayed
read completion is at the head of the delayed transaction queue, and the read data is at the
head of the read data queue. The initial value of this timer is program-mable through
configuration register. If the initiator does not repeat the read transaction and before the
master timeout timer expires (215 default), PI7C7300A discards the read transaction and
read data from its queues. PI7C7300A also conditionally asserts P_SERR# (see Section
7.4).
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| PI7C8150ANDE | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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