參數(shù)資料
型號(hào)： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 60/109頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 54 OF 109
09/25/03 Revision 1.09
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C7300A has write status to return, the following events occur:
!
PI7C7300A first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the
primary interface parity-error-response bit is set in the command register.
!
PI7C7300A sets the primary interface parity-error-detected bit in the status register.
!
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300A has write status to return, the following events occur:
!
PI7C7300A first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
!
PI7C7300A sets the secondary interface parity-error-detected bit in the secondary
status register.
!
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
PI7C7300A asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity-error-response bit is set in the command register of the primary
interface.
-
The parity-error-response bit is set in the bridge control register of the
secondary interface.
!
PI7C7300A completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
PI7C7300A asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity error response bit is set in the command register of the primary
interface.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
!
PI7C7300A completes the transaction normally.
相關(guān)PDF資料
PDF描述
PI7C7300DNAE IC PCI-PCI BRIDGE 3PORT 272-BGA
PI7C8140AMAE IC PCI-PCI BRIDGE 2PORT 128-QFP
PI7C8150ANDE IC PCI-PCI BRIDGE 2PORT 256-PBGA
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*