參數(shù)資料
型號: PI7C7300ANAE
廠商: Pericom
文件頁數(shù): 84/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝: 40
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 管件
安裝類型: 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 76 OF 109
09/25/03 Revision 1.09
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch
Configuration Register 1
Bit
Function
Type
Description
23:16
Header Type
R/O
Read as 81h to designate function 0 (multiple function PCI-to-PCI
bridge for secondary bus S1)
Configuration Register 2
Bit
Function
Type
Description
23:16
Header Type
R/O
Read as 01h to designate function 1 (single function PCI-to-PCI
bridge for secondary bus S2)
14.1.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
7:0
Primary Bus
Number
R/W
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
14.1.11
SECONDARY (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
15:8
Secondary (S1 or
S2) Bus Number
R/W
Indicates the number of the PCI bus to which the secondary
interface (S1 or S2) is connected. The value is set in software
during configuration.
Reset to 0
14.1.12
SUBORDINATE (S1 or S2) BUS NUMBER REGISTER – OFFSET
18h
Bit
Function
Type
Description
23:16
Subordinate
(S1 or S2) Bus
Number
R/W
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
14.1.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
Bit
Function
Type
Description
31:24
Secondary
Latency Timer
R/W
Designated in units of PCI bus clocks. Latency timer checks for
master accesses on the secondary bus interfaces that remain
unclaimed by any target.
Reset to 0
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