參數(shù)資料
型號： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 108/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 98 OF 109
09/25/03 Revision 1.09
master. The bus master can be either automatic test equipment or a component (i.e., PLD)
that interfaces to the TAP. The TAP controller changes state only in response to a rising
edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of
TCK controls the sequence of state changes. The TAP controller is initialized after
power-up by applying a low to the TRST# pin. In addition, the TAP controller can be
initialized by applying a high signal level on the TMS input for a minimum of five TCK
periods.
For greater detail on the behavior of the TAP controller, test logic in each controller state
and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test
Access Port and Boundary-Scan Architecture document (available from the IEEE).
Table 16-2 JTAG BOUNDARY REGISTER ORDER
Order
Pin Names
Type
Order
Pin Names
Type
0
ENUM#
output
60
P_STOP#
control
1
ENUM#
control
61
P_PERR#
bidir
2
HS_EN
input
62
P_PERR#
control
3
S_CFN#
input
63
P_LOCK#
input
4
S1_EN
input
64
P_SERR#
output
5
S2_EN
input
65
P_SERR#
control
6
SCAN_TM#
input
66
P_AD[13]
bidir
7
SCAN_EN
input
67
P_AD[13]
control
8
PLL_TM
input
68
P_AD[14]
bidir
9
BYPASS
input
69
P_AD[14]
control
10
S2_M66EN
input
70
P_AD[11]
bidir
11
P_RESET#
input
71
P_AD[11]
control
12
P_GNT#
input
72
P_AD[15]
bidir
13
P_REQ#
output
73
P_AD[15]
control
14
P_REQ#
control
74
P_AD[12]
bidir
15
P_AD[30]
bidir
75
P_AD[12]
control
16
P_AD[30]
control
76
P_AD[8]
bidir
17
P_AD[31]
bidir
77
P_AD[8]
control
18
P_AD[31]
control
78
P_CBE[1]
bidir
19
P_AD[27]
bidir
79
P_CBE[1]
control
20
P_AD[27]
control
80
P_AD[9]
bidir
21
P_AD[26]
bidir
81
P_AD[9]
control
22
P_AD[26]
control
82
P_AD[5]
bidir
23
P_AD[28]
bidir
83
P_AD[5]
control
24
P_AD[28]
control
84
P_M66EN
input
25
P_AD[29]
bidir
85
P_AD[6]
bidir
26
P_AD[29]
control
86
P_AD[6]
control
27
P_CBE[3]
bidir
87
P_AD[2]
bidir
28
P_CBE[3]
control
88
P_AD[2]
control
29
P_AD[24]
bidir
89
P_PAR
bidir
30
P_AD[24]
control
90
P_PAR
control
31
P_AD[25]
bidir
91
P_AD[0]
bidir
32
P_AD[25]
control
92
P_AD[0]
control
33
P_AD[23]
bidir
93
P_CBE[0]
bidir
34
P_AD[23]
control
94
P_CBE[0]
control
35
P_AD[22]
bidir
95
P_AD[7]
bidir
36
P_AD[22]
control
96
P_AD[7]
control
37
P_IDSEL
input
97
P_AD[10]
bidir
38
P_AD[21]
bidir
98
P_AD[10]
control
39
P_AD[21]
control
99
P_AD[1]
bidir
40
P_AD[20]
bidir
100
P_AD[1]
control
41
P_AD[20]
control
101
P_AD[3]
bidir
42
P_AD[19]
bidir
102
P_AD[3]
control
43
P_AD[19]
control
103
P_AD[4]
bidir
44
P_AD[18]
bidir
104
P_AD[4]
control
45
P_AD[18]
control
105
S1_AD[0]
bidir
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