參數(shù)資料
型號(hào)： PI7C7300ANAE
廠商： Pericom
文件頁(yè)數(shù)： 61/109頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 55 OF 109
09/25/03 Revision 1.09
7.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300A responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
!
PI7C7300A asserts P_PERR# two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
!
PI7C7300A sets the parity error detected bit in the status register of the primary
interface.
!
PI7C7300A captures and forwards the bad parity condition to the secondary bus.
!
PI7C7300A completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7300A responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
!
PI7C7300A asserts S_PERR# two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
!
PI7C7300A sets the parity error detected bit in the status register of the secondary
interface.
!
PI7C7300A captures and forwards the bad parity condition to the primary bus.
!
PI7C7300A completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
!
PI7C7300A sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
!
PI7C7300A asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The posted write parity error bit of P_SERR# event disable register is not set.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
-
The parity error response bit is set in the command register of the primary
interface.
-
PI7C7300A has not detected the parity error on the primary (initiator) bus which
the parity error is not forwarded from the primary bus to the secondary bus.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開(kāi)發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
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