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參數(shù)資料
| 型號(hào)： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁(yè)數(shù)： | 64/92頁(yè) |
| 文件大小： | 1823K |
| 代理商： | ORT82G5 |
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64
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Pin Information
(continued)
Recommended Power Supply Connections
Ideally, a board should have four separate power supplies as described below:
I
Tx-Rx digital auxiliary supplies.
The Tx-Rx digital and auxiliary power supply nodes should be supplied by a 1.5 V source. A single 1.5 V source
can supply power to Tx-Rx digital and auxiliary nodes.
I
Tx-Rx analog, guardband supplies.
A dedicated 1.5 V power supply should be provided to the analog power pins. This will allow the end user to mini-
mize noise. The guard band pins can also be sourced from the analog power supplies.
I
Tx output buffers.
the power supplies to the Tx output buffers should be isolated from the rest of the board power supplies. Special
care must be taken to minimize noise when providing board level power to these output buffers. The power supply
can be 1.5 V or 1.8 V depending on the end application.
I
Rx input buffers.
The power supplies to the Rx input buffers should be isolated from the rest of the board power supplies. Special
care must be taken to minimize noise when providing board level power to these input buffers. The power supply
can be 1.5 V or 1.8 V depending on the end application.
Recommended Power Supply Filtering Scheme
The board connections of the various SERDES V
DD
and V
SS
pins are critical to system performance. An example
demonstration board schematic is available at:
http://www.agere.com/netcom/platform/fpsc.html#ort82g5
Power supply filtering is in the form of:
I
A parallel bypass capacitor network consisting of 10 uf, 0.1 uf, and 1.0 uf caps close to the power source.
I
A parallel bypass capacitor network consisting of 0.01 uf and 0.1 uf close to the pin on the ORT82G5.
Example connections are shown in Figure 20. The naming convention for the power supply sources shown in the
figure are as follows:
I
Supply_1.5 V
—
Tx-Rx digital, auxiliary power pins.
I
Supply_V
DD
RX
—
Rx analog power pins, guard band power pins.
I
Supply V
DD
TX
—
Tx analog power pins.
I
Supply V
DD
IB
—
Input Rx buffer power pins.
I
Supply_V
DD
OB
—
Output Rx buffer power pins.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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