參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 40/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
40
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5 DB6 DB7
Default
Value
SERDES A Receive Channel Configuration Registers
30003
RXHR_AA
Receive Half Rate
Selection Bit, Bank
A, Channel A. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_AA
Receiver Power
Down Control Bit,
Bank A, Channel A.
When PWRDNR =
1, sections of the
receive hardware
are powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_AA
Receive Signal
Detect Alarm Over-
ride Bit, Bank A,
Channel A. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding
SDON alarm is sup-
pressed. SDOVRIDE
= 1 on device reset.
SDOVRIDE_AB
Receive Signal
Detect Alarm Over-
ride Bit, Bank A,
Channel B. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding
SDON alarm is sup-
pressed. SDOVRIDE
= 1 on device reset.
SDOVRIDE_AC
Receive Signal
Detect Alarm Over-
ride Bit, Bank A,
Channel C. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding
SDON alarm is sup-
pressed. SDOVRIDE
= 1 on device reset.
SDOVRIDE_AD
Receive Signal
Detect Alarm Over-
ride Bit, Bank A,
Channel D. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding
SDON alarm is sup-
pressed. SDOVRIDE
= 1 on device reset.
8B10BR_AA
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel A.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AA
Link State Machine
Enable Bit, Bank A,
Channel A. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30013
RXHR_AB
Receive Half Rate
Selection Bit, Bank
A, Channel B. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_AB
Receiver Power
Down Control Bit,
Bank A, Channel B.
When PWRDNR =
1, sections of the
receive hardware
are powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_AB
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel B.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AB
Link State Machine
Enalbe Bit, Bank A,
Channel B. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30023
RXHR_AC
Receive Half Rate
Selection Bit, Bank
A, Channel C. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_AC
Receiver Power
Down Control Bit,
Bank A, Channel C.
When PWRDNR =
1, sections of the
receive hardware
are powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_AC
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel C.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AC
Link State Machine
Enalbe Bit, Bank A,
Channel C. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
30033
RXHR_AD
Receive Half Rate
Selection Bit, Bank
A, Channel D. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_AD
Receiver Power
Down Control Bit,
Bank A, Channel D.
When PWRDNR =
1, sections of the
receive hardware
are powered down to
conserve power.
PWRDNR = 0 on
device reset.
8B10BR_AD
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel D.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AD
Link State Machine
Enalbe Bit, Bank A,
Channel D. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
—
—
—
04
相關(guān)PDF資料
PDF描述
ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
OS1001 Interface IC
OS1010 Optoelectronic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*