參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 3/92頁
文件大小： 1823K
代理商： ORT82G5
Agere Systems Inc.
3
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Table of Contents
List of Figures
Page
List of Tables
Page
Figure 1. ORT82G5 Block Diagram ..........................12
Figure 2. Internal High-Level Diagram of ORT82G5
Transceiver ..............................................................13
Figure 3. SERDES Functional Block Diagram for
One Channel ...........................................................17
Figure 4. ORT82G5 Transmit Path for a Single
SERDES Channel ...................................................18
Figure 5. ORT82G5 Receive Path for a Single
SERDES Channel ...................................................20
Figure 6. Fibre-Channel Link State Machine State
Diagram ...................................................................22
Figure 7. XAUI Link Synchronization State
Diagram ...................................................................24
Figure 8. Transmit MUX Block for a Single SERDES
Channel ...................................................................25
Figure 9. Receive DeMUX Block for a Single
SERDES Channel ...................................................26
Figure 10. Interconnect of Streams for FIFO ............27
Figure 11. Example of SERDES A Alignment and ...27
Figure 12. Example of SERDES A and B
Alignment ................................................................27
Figure 13. Example of Multiple Twin Channel ..........27
Figure 14. Multichannel Alignment FIFO Block for
a Single SERDES Channel .....................................28
Figure 15. De-Skew Lanes by Aligning /A/
Columns ..................................................................30
Figure 16. Block Diagram of Memory Block .............34
Figure 17. Minimum Timing Specs for Memory
Blocks-Write Cycle ..................................................35
Figure 18. Minimum Timing Specs for Memory
Blocks-Read Cycle ..................................................35
Figure 19. Receive Data Eye-diagram Template
(Differential) .............................................................55
Figure 20. Power Supply Filtering ............................65
Figure 21. Package Parasitics ..................................88
Table 1.
ORCA
ORT82G5 Family
—
Available
FPGA Logic ...............................................................1
Table 2. Preemphasis Settings ...................................19
Table 3. Transmit PLL Clock and Data Rates ............21
Table 4. Receive PLL Clock and Data Rates .............21
Table 5. XAUI Link Synchronization State
Diagram Notation
—
Variables ..................................23
Table 6. XAUI Link Synchronization State
Diagram
—
Functions ................................................23
Table 7. Multichannel Alignment Modes .....................29
Table 8. Definition of Bits of MRWDxy[39:0] ...............31
Table 9. High-Speed Serial Loopback Configuration .32
Table 10. Parallel Loopback Configuration .................33
Table 11. Structural Register Elements ......................36
Table 12. Memory Map ...............................................37
Table 13. Absolute Maximum Ratings ........................54
Table 14. Recommended Operating Conditions ........54
Table 15. Absolute Maximum Ratings ........................54
Table 16. Recommended Operating Conditions ........54
Table 17. Receiver Specifications ..............................55
Table 18. Reference Clock Specifications
(REFINP and REFINN) ............................................56
Table 19. Channel Output Jitter (1.25 Gbits/s) ...........56
Table 20. Channel Output Jitter (2.5 Gbits/s) .............56
Table 21. Serial Output Timing Levels (CML I/O) .......56
Table 22. Serial Input Timing and Levels (CML I/O) ...56
Table 23. FPGA Common-Function Pin
Description
..57
Table 24. FPSC Function Pin Description ..................60
Table 25. Power Supply Pin Groupings ......................63
Table 26. Embedded Core/FPGA Interface
Signal Description ...................................................66
Table 27. ORT82G5 680-Pin PBGAM Pinout .............70
Table 28.
ORCA
ORT82G5 Plastic Package
Thermal Guidelines .................................................88
Table 29.
ORCA
ORT82G5 Package Parasitics ........88
Table 30. Device Type Options ..................................91
Table 31. Temperature Options ..................................91
Table 32. Package Type Options ...............................91
Table 33.
ORCA
FPSC Package Matrix
(Speed Grades) .......................................................91
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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