參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 51/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
51
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Control Registers B
30900
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
B0
ENBYSYNC_B
A
Byte Align-
ments bank B,
channel A
LOOPENB_BA
Enable loop-
back mode for
bank B, chan-
nel A
ENBYSYNC_B
B
Byte Align-
ments bank B,
channel B
LOOPENB_BB
Enable loop-
back mode for
bank B, chan-
nel B
ENBYSYNC_B
C
Byte Align-
ments bank B,
channel C
LOOPENB_BC
Enable loop-
back mode for
bank B, chan-
nel C
ENBYSYNC_B
D
Byte Align-
ments bank B,
channel D
LOOPENB_BD
Enable loop-
back mode for
bank B, chan-
nel D
LCKREFN_BA
Lock receiver to
ref. clock for
bank B channel
A
NOWDALIGN_
BA
Defeats deMUX
alignment for
bank B, chan-
nel A
Reserved for future use
Reserved for future use
DOWDALIGN_
BD
Force new
deMUX word
alignment for
bank B, chan-
nel D
LCKREFN_BB
Lock receiver to
ref. clock for
bank B channel
B
NOWDALIGN_
BB
Defeats deMUX
alignment for
bank B, chan-
nel B
LCKREFN_BC
Lock receiver to
ref. clock for
bank B channel
C
NOWDALIGN_
BC
Defeats deMUX
alignment for
bank B, chan-
nel C
LCKREFN_BD
Lock receiver to
ref. clock for
bank B channel
D
NOWDALIGN_
BD
Defeats deMUX
alignment for
bank B, chan-
nel D
00
30901
B1
00
30902
30903
30910
B2
B3
B4
DOWDALIGN_
BA
Force new
deMUX word
alignment for
bank B, chan-
nel A
FMPU_SYNMODE_BA
Sync mode for BA
DOWDALIGN_
BB
Force new
deMUX word
alignment for
bank B, chan-
nel B
DOWDALIGN
_BC
Force new
deMUX word
alignment for
bank B, chan-
nel C
FMPU_SYNMODE_BB
Sync mode for BB
FMPU_STR_E
N_BA
Enable align-
ment function
for channel BA
FMPU_STR_E_
BB
Enable align-
ment function
for channel BB
FMPU_STR_E
N_BC
Enable align-
ment function
for channel BC
FMPU_STR_E
N_BD
Enable align-
ment function
for channel BD
00
30911
B5
FMPU_SYNMODE_BC
Sync mode for BC
Reserved for future use
Reserved for future use
FMPU_RESYN
C1_BD
Resync a single
channel, BD.
Write a 0, then
write a 1.
Write a 0, then
write a 1.
Reserved for future use
FMPU_SYNMODE_BD
Sync mode for BD
00
30912
30913
30920
B6
B7
B8
FMPU_RESYN
C1_BA
Resync a single
channel, BA.
Write a 0, then
write a 1.
FMPU_RESYN
C1_BB
Resync a single
channel, BB.
Write a 0, then
write a 1.
FMPU_RESYN
C1_BC
Resync a single
channel, BC.
Write a 0, then
write a 1.
FMPU_RESYN
C2_B1
Resync 2 chan-
nels, BA and
BB.
FMPU_RESYN
C2_B2
Resync 2 chan-
nels, BC and
BD.
Write a 0, then
write a 1.
FMPU_RESYN
C4_B
Resync 4 chan-
nels B[A:D].
Write a 0, then
write a 1.
XAUI_MODE B
Controls use of
XAUI link state
machine vs.
SERDES link
State machine
for bank B
00
30921
B9
NOCHALGN B
Bypass chan-
nel alignment
deMUXed data
directly to FPGA
for bank B
00
30922
30923
30930
30931
30932
30933
B10
B11
B12
B13
B14
B15
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
SCHAR_CHAN
Select channel to test
Reserved for future use
SCHAR_TXSEL
Select TX
option
SCHAR_ENA
Enable Charac-
terization of
SERDES B
00
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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