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參數(shù)資料
| 型號(hào)： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁數(shù)： | 30/92頁 |
| 文件大小： | 1823K |
| 代理商： | ORT82G5 |
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30
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Monitor the following status bits in registers 30805, 30905
I
DEMUXWAS_xx-They should be 1 indicating word alignment is achieved.
I
CH248_SYNCxx-They should be 1 indicating channel alignment. this is cleared by resync.
5.
Write a 1 to the appropriate resync registers 30820, 30920. Note that this assumes that the previous value of
the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the resync bits:
write a 0 and then write a 1.
Check out-of-sync and FIFO overflow status in registers 30814 (Bank A).
I
SYNC4_A_OOS, SYNC4_A_OVFL-by 4 alignment.
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SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A!_OOS, SYNC2_A!_OVFL-by 2 alignment.
Check out-of-sync status in registers 30914 (Bank 4).
I
SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment.
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SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment.
Check out-of-sync status in register 30A03
I
SYNC8_OOS, SYNC8_OVFL-by 8 alignment.
If out-of-sync bit is 1 or FIFO overflow is 1 then rewrite a 1 to the appropriate resync registers and monitor the
OOS and OVFL bits again. The resync operation requires a rising edge. Two writes are required to the resync
bits: write a 0 and then write a 1.
Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices
needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading
from a second alignment FIFO until all channels requesting alignment on the current device AND all channels
requesting alignment on the other device are aligned (as indicated on the K_CTRL character). This second
alignment FIFO will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the refer-
ence clock for both devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column. Fig-
ure 2 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that
at least ± 80 bits of skew compensation capability should be provided, which the ORT82G5 significantly exceeds.
2392(F)
Figure 15. De-Skew Lanes by Aligning /A/ Columns
LANE 0
K
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LANE 1
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LANE 2
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LANE 3
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LANE 0
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LANE 1
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LANE 2
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LANE 3
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A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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