參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 52/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
52
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
* For XAUISTAT_By (address 0x30904), the definitions of these bits are:
00—No synchronization.
01—Synchronization done.
10—Synchronization done no comma has been detected.
11—Not used.
Addr
(Hex)
Status Register B
30904
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
B16
XAUISTAT_BA*
Status of XAUI link state
machine for bank B, channel A
DEMUXWAS_
BA
Status of
deMUX word
alignment for
bank B, chan-
nel A
XAUISTAT_BB*
Status of XAUI link state
machine for bank B, channel B
DEMUXWAS_
BC
Status of
deMUX word
alignment for
bank B, chan-
nel C
XAUISTAT_BC*
Status of XAUI link state
machine for bank B, channel C
CH248_SYNC
_BA
Alignment
completed for
BA
XAUISTAT_BD*
Status of XAUI link state
machine for bank B, channel D
CH248_SYNC
_BC
Alignment
completed for
BC
00
30905
B17
DEMUXWAS_
BB
Status of
deMUX word
alignment for
bank B, chan-
nel B
DEMUXWAS_
BD
Status of
deMUX word
alignment for
bank B, chan-
nel D
CH248_SYNC
_BB
Alignment
completed for
BB
CH248_SYNC
_BD
Alignment
completed for
BD
00
30906
30907
30914
B18
B19
B20
Reserved for future use
Reserved for future use
SYNC2_B1_O
OS
Alignment out
of sync for BB
and BA
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
SYNC2_B1_O
VFL
Alignment
FIFO overflow
for BA and BB
SYNC2_B2_O
VFL
Alignment
FIFO overflow
for BD and BC
SYNC4_B_OV
FL
Alignment
FIFO overflow
for B[A:D]
SYNC2_B2_O
OS
Alignment out
of sync for BC
and BD
SYNC4_B_O
OS
Alignment out
of sync for
B[A:D]
Reserved for Future Use
00
30915
30916
30917
30924
30925
30926
30927
30934
30935
30936
30937
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
相關PDF資料
PDF描述
ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
OS1001 Interface IC
OS1010 Optoelectronic
相關代理商/技術參數(shù)
參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*