參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 46/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
46
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES B Transmit Channel Configuration Registers
30102
TXHR_BA
Transmit Half
Rate Selection
Bit, Bank B,
Channel A.
When TXHR =
1, the transmit-
ter samples data
on the falling
edge of the TBC
clock. When
TXHR = 0, the
transmitter sam-
ples data on the
falling edge of
the double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
TXHR_BB
Transmit Half
Rate Selection
Bit, Bank B,
Channel B.
When TXHR =
1, the transmit-
ter samples data
on the falling
edge of the TBC
clock. When
TXHR = 0, the
transmitter sam-
ples data on the
falling edge of
the double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
TXHR_BC
Transmit Half
Rate Selection
Bit, Bank B,
Channel C.
When TXHR =
1, the transmit-
ter samples data
on the falling
edge of the TBC
clock. When
TXHR = 0, the
transmitter sam-
ples data on the
falling edge of
the double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
PWRDNT_BA
Transmit Power-
down Control
Bit, Bank B,
Channel A.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BA
Transmit Preem-
phasis Selec-
tion Bit 0, Bank
B, Channel A.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BA
Transmit Preem-
phasis Selec-
tion Bit 1, Bank
B, Channel A.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BA
Transmit Half
Amplitude
Selection Bit,
Bank B, Chan-
nel A. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited
to half its ampli-
tude. Other-
wise, the
transmit output
buffer maintains
its full voltage
swing. HAMP =
0 on device
reset.
TBCKSEL_BA
Transmit Byte
Clock Selection
Bit, Bank B,
Channel A.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RINGOVR_BA
Transmit Ring
Counter Bubble
Detector Alarm
Override Con-
trol Bit, Bank B,
Channel A.
When RIN-
GOVR = 0, the
bubble detector
alarm is effec-
tive. Otherwise,
the bubble
detector alarm is
not effective.
RINGOVR = 0
on device reset.
8B10BT_BA
Transmit 8B/10B
Encoder Enable
Bit, Bank B,
Channel A.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
30112
PWRDNT_BB
Transmit Power-
down Control
Bit, Bank B,
Channel B.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BB
Transmit Preem-
phasis Selec-
tion Bit 0, Bank
B, Channel B.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BB
Transmit Preem-
phasis Selec-
tion Bit 1, Bank
B, Channel B.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BB
Transmit Half
Amplitude
Selection Bit,
Bank B, Chan-
nel B. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited
to half its ampli-
tude. Other-
wise, the
transmit output
buffer maintains
its full voltage
swing. HAMP =
0 on device
reset.
TBCKSEL_BB
Transmit Byte
Clock Selection
Bit, Bank B,
Channel B.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RINGOVR_BB
Transmit Ring
Counter Bubble
Detector Alarm
Override Con-
trol Bit, Bank B,
Channel B.
When RIN-
GOVR = 0, the
bubble detector
alarm is effec-
tive. Otherwise,
the bubble
detector alarm is
not effective.
RINGOVR = 0
on device reset.
8B10BT_BB
Transmit 8B/10B
Encoder Enable
Bit, Bank B,
Channel B.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
30122
PWRDNT_BC
Transmit Power-
down Control
Bit, Bank B,
Channel C.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BC
Transmit Preem-
phasis Selec-
tion Bit 0, Bank
B, Channel C.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BC
Transmit Preem-
phasis Selec-
tion Bit 1, Bank
B, Channel C.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BC
Transmit Half
Amplitude
Selection Bit,
Bank B, Chan-
nel C. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited
to half its ampli-
tude. Other-
wise, the
transmit output
buffer maintains
its full voltage
swing. HAMP =
0 on device
reset.
TBCKSEL_BC
Transmit Byte
Clock Selection
Bit, Bank B,
Channel C.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RINGOVR_BC
Transmit Ring
Counter Bubble
Detector Alarm
Override Con-
trol Bit, Bank B,
Channel C.
When RIN-
GOVR = 0, the
bubble detector
alarm is effec-
tive. Otherwise,
the bubble
detector alarm is
not effective.
RINGOVR = 0
on device reset.
8B10BT_BC
Transmit 8B/10B
Encoder Enable
Bit, Bank B,
Channel C.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
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