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參數(shù)資料
| 型號： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁數(shù)： | 21/92頁 |
| 文件大?。?/td> | 1823K |
| 代理商： | ORT82G5 |
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Agere Systems Inc.
21
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed
Description
(continued)
8b/10b Encoding/Decoding
The 8b/10b encoder encodes the incoming 8-bit data
into a 10-bit format according to the
IEEE
802.3z stan-
dard. Input pins SRBDx<7:0> (where x is a placeholder
for one of the letters, A
—
D) are used for 8 bit unen-
coded data and SRBDx<8> is used as the K_control
input to indicate whether the 8 data bits need to be
encoded as special characters (K_control = 1) or as
data characters (K_control = 0). When the encoder is
bypassed SRBDx<9:0>serve as the data bits for the
10-bit encoded data.
Within the definition of the 8b/10b transmission code,
the bit positions of the 10-bit encoded transmission
characters are labeled as a, b, c, d, e, i, f, g, h, and j in
that order. Bit a corresponds to SRBDx[0], bit b to
SRBDx[1], bit c to SRBDx[2], bit d to SRBDx[3], bit e to
SRBDx[4], bit i to SRBDx[5], bit f to SRBDx[6], bit g to
SRBDx[7], bit h to SRBDx[8], and bit j to SRBDx[9].
The data SRBDx[9:0] is transmitted serially with
SRBDx[0] transmitted first and SRBDx[9] transmitted
last.
For an 8-bit unencoded data, the 8-bit unencoded data
SRDBx[7:0] is represented as HGF EDCBA SRDBx[8]
represents the K_CTRL bit and SRDBx[9] is unused
(tied to logic 0). SRBDx[0] is still transmitted first and
SRBDx[9] transmitted last.
SERDES Transmit and Receive PLLs
The high-speed transmit and receive serial data can
operate at 1.0
—
1.25 Gbits/s or 2.0
—
3.125 Gbits/s
depending on the state of the control bits from the
microprocessor interface. Table 3 shows the relation-
ship between the data rates, the reference clock, and
the transmit TWCKx clocks.
The receiver section receives high-speed serial data at
its differential CML input port. These data are fed to the
clock recovery section which generates a recovered
clock and retimes the data. This means that the receive
clocks are asynchronous between channels. The
retimed data are deserialized and presented as a 10-bit
encoded or a 8-bit unencoded parallel data on the out-
put port. RWCKx receive byte clocks are available syn-
chronous with the parallel words. The receiver also
recognizes the comma characters and aligns the bit
stream to the proper word boundary.
Table 4 shows the relationship between the data rates,
the reference clock, and the RWCKx clocks.
For more information on the reference clock input
requirements and connections to either single ended or
differential inputs, see the
LU6X14FT SERDES Macro-
cell
Data sheet or the associated reference clock appli-
cation note.
Table 3. Transmit PLL Clock and Data Rates
Note: The selection of full-rate or half-rate for a given reference clock
speed is set by a bit in the transmit control register and can be
set per channel.
Table 4. Receive PLL Clock and Data Rates
Note: The selection of full-rate or half-rate for a given reference clock
speed is set by a bit in the receive control register and can be
set per channel.
Reference Clock
The differential reference clock is distributed to all four
channels. Each channel has a differential buffer to iso-
late the clock from the other channels. The input clock
is preferably a differential signal; however, the device
can operate with a single-ended input. The input refer-
ence clock directly impacts the transmit data eye, so
the clock should have low jitter. In particular, jitter com-
ponents in the dc
—
5 MHz range should be minimized.
Note:
The reference clock, REFCLK, is equivalent to
REFINP and REFINN; throughout the text simply
refer to the reference clock as REFCLK.
Data Rate
Reference
Clock
100 MHz
125 MHz
100 MHz
125 MHz
156 MHz
TCK78[A, B]
Clock
25 MHz
31.25 MHz
50 MHz
62.5 MHz
78 MHz
Rate
1.0 Gbits/s
1.25 Gbits/s
2.0 Gbits/s
2.5 Gbits/s
3.125 Gbits/s
Half
Half
Full
Full
Full
Data Rate
Reference
Clock
100 MHz
125 MHz
100 MHz
125 MHz
156 MHz
RWCKx
Clocks
25 MHz
31.25 MHz
50 MHz
62.5 MHz
78 MHz
Rate
1.0 Gbits/s
1.25 Gbits/s
2.0 Gbits/s
2.5 Gbits/s
3.125 Gbits/s
Half
Half
Full
Full
Full
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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