參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 34/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
34
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Operational Mode Full Loopback Test Using The PRBS Generator/Checker
The operational mode full loopback test forms one of the normal operational modes of the device. The loopback
can be either internal to the device or external to it. To perform the test with internal loopback, the LOOPENB pin
should be set to a logic 1. The test includes the PRBS generator in the transmit path and the PRBS checker in the
receive path. In this case, the device is placed in its normal operational mode with all the functional blocks in the
transmit and the receive path active. The transmit data is generated by an LFSR. The generated word is then seri-
alized and looped back (either internally or externally) to the receiver. The receiver first deserializes the 8-bit word
to regenerate the transmitted 8-bit word. The PRBS checker on the receiver compares the regenerated 8-bit word
against the transmitted 8-bit word on a word by word basis and signals a mismatch by asserting a PRBSCHK alarm
status bit. During this test, the receiver regenerated 8-bit words can also be observed on the device output ports.
The PRBS checker contains a watchdog timer which asserts the time-out alarm status bit, PRBSTOUT, if the
PRBS test cannot progress beyond its start state within a reasonable time interval. This time interval is set by the
precision of the watchdog timer. Both the PRBSCHK and the PRBSTOUT alarms can generate an interrupt if their
corresponding masks are disabled.
ASB Memory Blocks
This section describes the memory blocks in the embedded core. Note that although the memory blocks are in the
embedded core part of the chip, they do not interact with the rest of the embedded core circuits. They are stand-
alone blocks designed specifically to increase RAM capacity in the ORT82G5 chip, and will be used by the soft IP
cores in the FPGA.
There are two independent memory blocks in the embedded core. These are in addition to the block RAMs found in
the FPGA portion of the ORT82G5. A block diagram of a memory block is shown in Figure 16. Each memory block
has a capacity of 4K word by 36 bit. It has one read port and one write port and four byte-write-enable (active-low)
signals. The read data from the memory block is registered so that it works as a pipelined synchronous memory
block. A block diagram of the memory block in shown below in Figure 16.The minimum timing specifications are
shown in Figure 18.
2270(F)
Figure 16. Block Diagram of Memory Block
4K x 36
MEMORY BLOCK
(1 OF 2)
D_x[35:0]
CKW_x
CSWA_x
CSWB_x
AW_x[10:0]
BYTEWN_x[3]
BYTEWN_x[2]
BYTEWN_x[1]
BYTEWN_x[0]
BW[35,31:24]
BW[34,23:16]
BW[33,15:8]
BW[32,7:0]
CKR_x
CSR_x
AR_x[10:0]
Q_x[35:0]
WRITE PORTS
READ PORTS
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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