參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 42/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
42
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Global Control Register (Acts on Channels A, B, C, and D)
30005
GPRBS_A
Global Enable.
The GPRBS bit
globally enables
the PRBS gen-
erators and
checkers all four
channels of
SERDES A
when GPRBS =
1. GPRBS = 0
on device reset.
GMASK_A
Global Mask.
The GMASK
globally masks
all the channel
alarms of SER-
DES A when
GMASK = 1.
This prevents all
the transmit and
receive alarms
from generat-
ing an interrupt.
GMASK = 1 on
device reset.
GSWRST_A
RESET Func-
tion. The
GSWRST bit
provides the
same function
as the hardware
reset for the
transmit and
receive sec-
tions of all four
channels of
ASERDES A,
except that the
device configu-
ration settings
are not affected
when GSWRST
is asserted.
GSWRST = 0
on device reset.
This is not a
self-clearing bit.
Once set, it
must be cleared
by writing a 0 to
it.
GPWRDNT_A
Powerdown
Transmit Func-
tion. When
GPWRDNT = 1,
sections of the
transmit hard-
ware for all four
channels of
SERDES A are
powered down
to conserve
power.
GPWRDNT = 0
on device reset.
GPWRDNR_A
Powerdown
Receive Func-
tion. When
GPWRDNR =
1, sections of
the receive
hardware for all
four channels of
SERDES A are
powered down
to conserve
power.
GPWRDNR = 0
on device reset.
GTRISTN_
A
Active-Low
TRISTN
Function.
When
GTRISTN =
0, the
CMOS out-
put buffers
for SER-
DES A are
3-stated.
GTRISTN =
1 on device
reset.
—
GTESTEN_A
Test Enable
Control. When
GTESTEN = 1,
the transmit
and receive
sections of all
four channels
of SERDES A
are placed in
test mode.
GTESTEN = 0
on device reset.
022
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