參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 29/92頁(yè)
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
29
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed
Description
(continued)
The use of the FIFO is controlled by configuration bits,
and the raw demultiplexed data can also be sent to the
FPGA directly, by passing the alignment FIFO. The
control register bits for alignment FIFO in ORT82G5
are described below.
Table 7. Multichannel Alignment Modes
where xx is one of A[A:D] and B[A:D].
To align all eight channels:
I
FMPU_SYNMODE_A[A:D] = 11
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FMPU_SYNMODE_B[A:D] = 11
To align all four channels in SERDES A:
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FMPU_SYNMODE_A[A:D] = 10
To align two channels in SERDES A:
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FMPU_SYNMODE_A[A:B] = 01 for channel AA and
AB
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FMPU_SYNMODE_A[C:D] = 01 for channel AC and
AD
Similar alignment can be defined for SERDES B.
To enable/disable synchronization signal of individual
channel within a multi-channel alignment group:
I
FMPU_STR_EN_xx = 1 enabled
I
FMPU_STR_EN_xx = 0 disabled
where xx is one of A[A:D] and B[A:D].
To re-synchronize a multi-channel alignment group set
the following bit to zero, and then set it to 1.
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FMPU_RESYNC8 for eight channel A[A:D] and
B[A:D]
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FMPU_RESYNC4A for quad channel A[A:D]
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FMPU_RESYNC2A1 for twin channel A[A:B]
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FMPU_RESYNC2A2 for twin channel A[C:D]
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FMPU_RESYNC4B for quad channel B[A:D]
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FMPU_RESYNC2B1 for twin channel B[A:B]
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FMPU_RESYNC2B2 for twin channel B[C:D]
To resynchronize an independent channel (resetting
the write and the read pointer of the FIFO) set the fol-
lowing bit to zero, and then set it to 1.
I
FMPU_RESYNC1_xx where xx is one of A[A:D] and
B[A:D]
A two-to-one multiplexor is used to select between
aligned or nonaligned data to be sent to the FPGA on
MRWDxy[39:0]. With x representing the bank (place-
holder for A or B) and y representing the channel
(placeholder for A, B, C or D), the 40-bit MRWDxy[39:0]
is allocated as shown in Table 8.
Alignment Sequence
1.
Follow steps 1 and 2 in the start up sequence
described previously.
Initiate a SERDES software reset by setting the
SWRST bit to 1 and then to 0. Note that, any
changes to the SERDES configuration bits should
be followed by a software reset.
Wait for 3 ms. REFCLK_[P N] should be toggling
by this time. During this time, configure the follow-
ing registers.
2.
3.
Set the following bits in registers 30820, 30920
I
XAUI_MODEx-set to 1 for XAUI mode or keep the
default value of 0.
Enable channel alignment by setting sync bits in
registers 30811, 30911
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FMPU_SYNMODE_xx. Set to appropriate val-
ues for 2, 4, or 8 alignment.
Set RCLKSELx and TCKSELx bits in registers
30A00.
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RCKSELx-choose clock source for 78 MHz
RCK78x.
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TCKSELx-Choose clock source for 78 MHz
TCK78x.
4.
Send data on serial links. Monitor the following sta-
tus/alarm bits:
Monitor the following alarm bits in registers 30000,
30010, 30020, 30030, 30100, 30110, 30120,
30130.
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LKI-PLL lock indicator. A 1 indicates that PLL has
achieved lock.
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SDON-signal detect output indicator. A 0 indi-
cates active data.
Monitor the following status bits in registers 30804,
30904
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XAUISTAT_xx-In XAUI mode, they should be 01
or 10.
Register Bits
FMPU_SYNMODE_xx
00
01
10
11
Mode
No multichannel alignment.
Twin channel alignment.
Quad channel alignment.
Eight channel alignment.
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