參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 18/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
18
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
SERDES Transmit Path (FPGA
→
Backplane)
The transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port from
the MUX/deMUX block. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to
synthesize the internal high-speed serial bit clock.
The serialized data are available at the differential CML output terminated in 50
or 75
to drive either an optical
transmitter, coaxial media, or circuit board/backplane.
The STBDx[8:0] (where x is a placeholder for one of the letters, A
—
D) ports carry unencoded character data in this
design. The time-division multiplexer in the ORT82G5 is only 9 bits wide. The 10th bit (STBDx[9]) of each data lane
into the SERDES is held constant. It is not possible to use the ORT82G5 for normal data communication without
enabling SERDES 8b/10b encoding.
The functional mode uses the STBCx311 SERDES output as the reference clock. The frequency of this clock will
depend on the half-rate/full-rate control bit in the SERDES; and the frequency of the REFCLK ports and/or that of
the high-speed serial data. The SERDES TBCKSEL control bit must be configured to a 0 for each channel in order
for this clocking strategy to work.
A falling edge on the STBC311x clock port will cause a new data character to be sent from STBDx[9:0] to the SER-
DES block with a latency of 5 STBC311x clock cycles at the high-speed serial output.
2264(F)
Figure 4. ORT82G5 Transmit Path for a Single SERDES Channel
10:1
MULTIPLEXER
100
—
156 MHz
REFERENCE
PLL
8B/10B
ENCODER
CLOCK
TRANSMIT DATA
1.0
—
3.125 Gbits/s
4:1
MULTIPLEXER
(X 9)
10
8
EMBEDDED CORE
DATA BYTE
STBDx[7:0]
K-CONTROL
STBDx{8]
9
GROUND
STBDx[9]
STBC311x
SERDES
BLOCK
MUX/DEMUX
BLOCK
HDOUTPx,
HDOUTNx
p
q
r
s
t
x
y
z
STBDx[9:0]
STBC311x
HDOUTx
p4p5p6p7p8p9
p0p1p2p3
LATENCY =
5 STBC311x CLOCKS
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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