參數(shù)資料
型號(hào)： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 37/92頁(yè)
文件大小： 1823K
代理商： ORT82G5
Agere Systems Inc.
37
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12 details the memory map for the ASIC core of the ORT82G5 device. This table shows the databus oriented
for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the user master interface is used to preform opera-
tions to the ASIC core then the databus must be used in the opposite notation, where DB7 is the MSB and DB0 is
the LSB.
Table 12. Memory Map
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Alarm Registers (Read Only)
30000
SDON_AA
Receive Signal
Detect Output, Bank
A, Channel A. When
SDON_AA = 0, then
active data is
present.
LKI_AA
Receive PLL Lock
Indication, Bank A,
Channel A. When
LKI_AA = 1, then
PLL receive is
locked.
PRBSCHK_AA
PRBS Check Pass/
Fail Indication, Bank
A, Channel A. When
PRBSCHK_AA = 0,
then it is a pass indi-
cation.
PRBSTOUT_AA
PRBS Checker Watch-
dog Timer Time-Out
Alarm, Bank A, Channel
A. When
PRBSTOUT_AA = 1,
then timeout has
occurred.
PRBSTOUT_AB
PRBS Checker Watch-
dog Timer Time-Out
Alarm, Bank A, Channel
B. When
PRBSTOUT_AB = 1,
then timeout has
occurred.
PRBSTOUT_AC
PRBS Checker Watch-
dog Timer Time-Out
Alarm, Bank A, Channel
C. When
PRBSTOUT_AC = 1,
then timeout has
occurred.
PRBSTOUT_AD
PRBS Checker Watch-
dog Timer Time-Out
Alarm, Bank A, Channel
D. When
PRBSTOUT_AD = 1,
then timeout has
occurred.
—
—
—
—
00
30010
SDON_AB
Receive Signal
Detect Output, Bank
A, Channel B. When
SDON_AB = 0, then
active data is
present.
LKI_AB
Receive PLL Lock
Indication, Bank A,
Channel B. When
LKI_AB = 1, then
PLL receive is
locked.
PRBSCHK_AB
PRBS Check Pass/
Fail Indication, Bank
A, Channel B. When
PRBSCHK_AB = 0,
then it is a pass indi-
cation.
—
—
—
—
00
30020
SDON_AC
Receive Signal
Detect Output, Bank
A, Channel C. When
SDON_AC = 0, then
active data is
present.
LKI_AC
Receive PLL Lock
Indication, Bank A,
Channel C. When
LKI_AC = 1, then
PLL receive is
locked.
PRBSCHK_AC
PRBS Check Pass/
Fail Indication, Bank
A, Channel C. When
PRBSCHK_AC = 0,
then it is a pass indi-
cation.
—
—
—
—
00
30030
SDON_AD
Receive Signal
Detect Output, Bank
A, Channel D. When
SDON_AD = 0, then
active data is
present.
LKI_AD
Receive PLL Lock
Indication, Bank A,
Channel D. When
LKI_AD = 1, then
PLL receive is
locked.
PRBSCHK_AD
PRBS Check Pass/
Fail Indication, Bank
A, Channel D. When
PRBSCHK_AD = 0,
then it is a pass indi-
cation.
—
—
—
—
00
SERDES A Alarm Mask Registers
30001
MSDON_AA
Mask Receive Sig-
nal Detect Output,
Bank A, Channel A.
MLKI_AA
Mask Receive PLL
Lock Indication, Bank
A, Channel A.
MPRBSCHK_AA.
Mask PRBS Check
Pass/Fail Indication,
Bank A, Channel A.
MPRBSTOUT_AA
Mask PRBS Checker
Watchdog Timer Time-
Out Alarm, Bank A,
Channel A.
MPRBSTOUT_AB
Mask PRBS Checker
Watchdog Timer Time-
Out Alarm, Bank A,
Channel B.
MPRBSTOUT_AC
Mask PRBS Checker
Watchdog Timer Time-
Out Alarm, Bank A,
Channel C.
MPRBSTOUT_AD
Mask PRBS Checker
Watchdog Timer Time-
Out Alarm, Bank A,
Channel D.
—
—
—
—
FF
30011
MSDON_AB
Mask Receive Sig-
nal Detect Output,
Bank A, Channel B.
MLKI_AB
Mask Receive PLL
Lock Indication, Bank
A, Channel B.
MPRBSCHK_AB.
Mask PRBS Check
Pass/Fail Indication,
Bank A, Channel B.
—
—
—
—
FF
30021
MSDON_AC
Mask Receive Sig-
nal Detect Output,
Bank A, Channel C.
MLKI_AC
Mask Receive PLL
Lock Indication, Bank
A, Channel C.
MPRBSCHK_AC.
Mask PRBS Check
Pass/Fail Indication,
Bank A, Channel C.
—
—
—
—
FF
30031
MSDON_AD
Mask Receive Sig-
nal Detect Output,
Bank A, Channel D.
MLKI_AD
Mask Receive PLL
Lock Indication, Bank
A, Channel D.
MPRBSCHK_AD.
Mask PRBS Check
Pass/Fail Indication,
Bank A, Channel D.
—
—
—
—
FF
相關(guān)PDF資料
PDF描述
ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
OS1001 Interface IC
OS1010 Optoelectronic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*