參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 49/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
49
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES B Common Transmit and Receive Channel Configuration Registers
30104
PRBS_BA
Transmit and
Receive PRBS
Enable Bit,
Bank B, Chan-
nel A. When
PRBS = 1, the
PRBS genera-
tor on the trans-
mitter and the
PRBS checker
on the receiver
are enabled.
PRBS = 0 on
device reset.
PRBS_BB
Transmit and
Receive PRBS
Enable Bit,
Bank B, Chan-
nel B. When
PRBS = 1, the
PRBS genera-
tor on the trans-
mitter and the
PRBS checker
on the receiver
are enabled.
PRBS = 0 on
device reset.
PRBS_BC
Transmit and
Receive PRBS
Enable Bit,
Bank B, Chan-
nel C. When
PRBS = 1, the
PRBS genera-
tor on the trans-
mitter and the
PRBS checker
on the receiver
are enabled.
PRBS = 0 on
device reset.
PRBS_BD
Transmit and
Receive PRBS
Enable Bit,
Bank B, Chan-
nel D. When
PRBS = 1, the
PRBS genera-
tor on the trans-
mitter and the
PRBS checker
on the receiver
are enabled.
PRBS = 0 on
device reset.
MASK_BA
Transmit and Receive
Alarm Mask Bit, Bank
B, Channel A. When
MASK = 1, the trans-
mit and receive
alarms of a channel
are prevented from
generating an inter-
rupt. This MASK bit
overrides the individ-
ual alarm mask bits in
the Alarm Mask Reg-
isters. MASK = 1 on
device reset.
MASK_BB
Transmit and Receive
Alarm Mask Bit, Bank
B, Channel B. When
MASK = 1, the trans-
mit and receive
alarms of a channel
are prevented from
generating an inter-
rupt. This MASK bit
overrides the individ-
ual alarm mask bits in
the Alarm Mask Reg-
isters. MASK = 1 on
device reset.
MASK_BC
Transmit and Receive
Alarm Mask Bit, Bank
B, Channel C. When
MASK = 1, the trans-
mit and receive
alarms of a channel
are prevented from
generating an inter-
rupt. This MASK bit
overrides the individ-
ual alarm mask bits in
the Alarm Mask Reg-
isters. MASK = 1 on
device reset.
MASK_BD
Transmit and Receive
Alarm Mask Bit, Bank
B, Channel D. When
MASK = 1, the trans-
mit and receive
alarms of a channel
are prevented from
generating an inter-
rupt. This MASK bit
overrides the individ-
ual alarm mask bits in
the Alarm Mask Reg-
isters. MASK = 1 on
device reset.
SWRST_BA
Transmit and Receive
Software Reset Bit,
Bank B, Channel A.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
configuration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
SWRST_BB
Transmit and Receive
Software Reset Bit,
Bank B, Channel B.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
configuration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
SWRST_BC
Transmit and Receive
Software Reset Bit,
Bank B, Channel C.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
configuration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
SWRST_BD
Transmit and Receive
Software Reset Bit,
Bank B, Channel D.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
configuration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
—
—
—
—
TESTEN_BA
Transmit and Receive Test
Enable Bit, Bank B, Channel A.
When TESTEN = 1, the trans-
mit and receive sections are
placed in test mode. TESTEN
= 0 on device reset. When the
global test enable bit GTES-
TEN = 0, the individual channel
test enable bits are used to
selectively place a channel in
test or normal mode. When
GTESTEN = 1, all channels are
set to test mode regardless of
their TESTEN setting.
TESTEN_BB
Transmit and Receive Test
Enable Bit, Bank B, Channel B.
When TESTEN = 1, the trans-
mit and receive sections are
placed in test mode. TESTEN
= 0 on device reset. When the
global test enable bit GTES-
TEN = 0, the individual channel
test enable bits are used to
selectively place a channel in
test or normal mode. When
GTESTEN = 1, all channels are
set to test mode regardless of
their TESTEN setting.
TESTEN_BC
Transmit and Receive Test
Enable Bit, Bank B, Channel C.
When TESTEN = 1, the trans-
mit and receive sections are
placed in test mode. TESTEN
= 0 on device reset. When the
global test enable bit GTES-
TEN = 0, the individual channel
test enable bits are used to
selectively place a channel in
test or normal mode. When
GTESTEN = 1, all channels are
set to test mode regardless of
their TESTEN setting.
TESTEN_BD
Transmit and Receive Test
Enable Bit, Bank B, Channel D.
When TESTEN = 1, the trans-
mit and receive sections are
placed in test mode. TESTEN
= 0 on device reset. When the
global test enable bit GTES-
TEN = 0, the individual channel
test enable bits are used to
selectively place a channel in
test or normal mode. When
GTESTEN = 1, all channels are
set to test mode regardless of
their TESTEN setting.
02
30114
—
—
—
—
02
30124
—
—
—
—
02
30134
—
—
—
—
02
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