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參數(shù)資料
| 型號(hào)： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁數(shù)： | 19/92頁 |
| 文件大小： | 1823K |
| 代理商： | ORT82G5 |
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Agere Systems Inc.
19
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Transmit Preemphasis and Amplitude Control
The transmitter
’
s CML output buffer is terminated on-chip to optimize the data eye as well as to reduce the number
of discrete components required. The differential output swing reaches a maximum of 1.2 V
PP
in the normal ampli-
tude mode. A half amplitude mode can be selected via configuration register bit HAMP Half amplitude mode can
be used to reduce power dissipation when the transmission medium has minimal attenuation.
A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi-
mize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted
over backplanes or low-quality coax cables. The degree of preemphasis can be programmed with a two-bit control
from the microprocessor interface as shown in Table 2. The high-pass transfer function of the preemphasis circuit
is shown below, where the value of a is shown in Table 2.
H(z) = (1
–
az
–
1
)
Table 2. Preemphasis Settings
SERDES Receive Path (Backplane
→
FPGA)
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as a 10-bit encoded or a
8-bit unencoded parallel data on the output port. Two-phase receive byte clocks are available synchronous with the
parallel words. The receiver also recognizes the comma characters and aligns the bit stream to the proper word
boundary.
The receive PLL has two modes of operation as follows: lock to reference and lock to data with retiming. When no
data or invalid data is present on the HDINP and HDINN pins, the receive VCO will not lock to data and its fre-
quency can drift outside of the nominal ±100 ppm range. Under this condition, the receive PLL will lock to REFCLK
for a fixed time interval and then will attempt to lock to receive data. The process of attempting to lock to data, then
locking to clock will repeat until valid input data exists. There is also a control register bit per channel to force the
receive PLL to always lock to the reference clock.
The activity detector monitors the presence of data on each of the differential high-speed input pins. In the absence
of amplitude qualified data on the inputs the chip automatically goes into sleep mode. This function can, however,
be disabled through the control interface.
The PRBS checker is a built-in bit error rate tester (BERT). When enabled, it produces a one-bit PRBSCHK output
to indicate whether there was an error in the loopback data.
PE1
0
0
1
1
PE0
0
1
0
1
Amount of Preemphasis (a)
0% (No Preemphasis)
12.5%
12.5%
25%
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參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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