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參數(shù)資料
| 型號(hào)： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進(jìn)文化基金 |
| 文件頁數(shù)： | 32/92頁 |
| 文件大?。?/td> | 1823K |
| 代理商： | ORT82G5 |
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32
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed Description
(continued)
Loopback Modes
The device can be exercised in four possible loopback modes. These loopback modes are identified as:
I
High-speed serial loopback
I
Parallel loopback at the SERDES boundary
I
Parallel loopback at MUX/deMUX boundary excluding SERDES
I
Operational mode full loopback using the PRBS generator/checker
These four loopback modes are described next.
High-Speed Serial Loopback
The high-speed serial loopback involves the transmit signal at the serial interface being looped back internally to
the receive circuitry. The serial loopback path does not include the high-speed input and output buffers. The
HDOUTP HDOUTN outputs are active in this loopback mode, but the CML input buffers are powered down. The
data are sourced at the LDIN[9:0] pins and detected at the LDOUT[9:0] pins. The device is otherwise in its normal
mode of operation. The data rate selection bits, TXHR and RXHR, in the channel configuration registers must be
configured to carry the same value and the PRBS Generator and Checker are excluded by setting the PRBS con-
figuration bit to 0. The 8b/10b encoder/decoder can optionally be configured into or out of the loopback path. The
following Table 9 illustrates the control interface register configuration for the high-speed serial loopback.
Table 9. High-Speed Serial Loopback Configuration
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
30004, 30014, 30024,
30034, 30104, 30114,
30124, 30134
30004, 30014, 30024,
30034, 30104, 30114,
30124, 30134
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the
same value.
Bit 7 = 0 or 1
8B10BT
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded
from the loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to the same value.
Set to 0 or 1. TXHR and RXHR bits must be set to the
same value.
Bit 0 = 0 or 1
RXHR
Bit 3 = 0 or 1
8B10BR
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded
from the loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to the same value.
Set to 0.
Bit 0 = 0
PRBS
Bit 7 = 1
TESTEN
Set to 1 if the loopback is done on a per-channel basis.
However, if the loopback is done globally on all the four
channels, this bit can be set to 0 but bit 7 of register 5
must be set to 1.
Set to 1 if the loopback is done globally on all four
channels.
Set to 00000.
30005, 30105
Bit 7 = 1
GTESTEN
30006, 30106
Bits[4:0] =
00000
—
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