參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 43/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
Agere Systems Inc.
43
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
Control Registers A
30800
A0
ENBYSYNC_
AA
Byte Align-
ments bank
A, channel A
ENBYSYNC_
AB
Byte Align-
ments bank
A, channel B
ENBYSYNC_
AC Byte
Alignments
bank A, chan-
nel C
ENBYSYNC_
AD
Byte Align-
ments bank
A, channel D
LCKREFN_A
A
Lock receiver
to ref. clock
for bank A
channel A
NOWDALIGN
_AA
Defeats
deMUX align-
ment for bank
A, channel A
Reserved for future use
Reserved for future use
DOWDALIGN
_AD
Force new
deMUX word
alignment for
bank A, chan-
nel D
FMPU_SYNMODE_AB
Sync mode for AB
LCKREFN_A
B
Lock receiver
to ref. clock
for bank A
channel B
NOWDALIGN
_AB
Defeats
deMUX align-
ment for bank
A, channel B
LCKREFN_A
C
Lock receiver
to ref. clock
for bank A
channel C
NOWDALIGN
_AC
Defeats
deMUX align-
ment for bank
A, channel C
LCKREFN_A
D
Lock receiver
to ref. clock
for bank A
channel D
NOWDALIGN
_AD
Defeats
deMUX align-
ment for bank
A, channel
00
30801
A1
LOOPENB_A
A
Enable loop-
back mode for
bank A, chan-
nel A
LOOPENB_A
B
Enable loop-
back mode for
bank A, chan-
nel B
LOOPENB_A
C
Enable loop-
back mode for
bank A, chan-
nel C
LOOPENB_A
D
Enable loop-
back mode for
bank A, chan-
nel D
00
30802
30803
30810
A2
A3
A4
DOWDALIGN
_AA
Force new
deMUX word
alignment for
bank A, chan-
nel A
FMPU_SYNMODE_AA
Sync mode for AA
DOWDALIGN
_AB
Force new
deMUX word
alignment for
bank A, chan-
nel B
DOWDALIGN
_AC
Force new
deMUX word
alignment for
bank A, chan-
nel C
FMPU_STR_
EN _AA
Enable align-
ment function
for channel
AA
FMPU_STR_
EN _AB
Enable align-
ment function
for channel
AB
FMPU_STR_
EN_AC
Enable align-
ment function
for channel
AC
FMPU_STR_
EN_AD
Enable align-
ment function
for channel
AD
00
30811
A5
FMPU_SYNMODE_AC
Sync mode for AC
Reserved for future use
Reserved for future use
FMPU_RESY
NC1_AD
Resync a sin-
gle channel,
AD.
Write a 0,
then write a 1.
then write a 1.
FMPU_SYNMODE_AD
Sync mode for AD
00
30812
30813
30820
A6
A7
A8
FMPU_RESY
NC1_AA
Resync a sin-
gle channel,
AA.
Write a 0,
then write a 1.
FMPU_RESY
NC1_AB
Resync a sin-
gle channel,
AB.
Write a 0,
then write a 1.
FMPU_RESY
NC1_AC
Resync a sin-
gle channel,
AC.
Write a 0,
then write a 1.
FMPU_RESY
NC2_A1
Resync 2
channels, AA
and AB.
Write a 0,
FMPU_RESY
NC2A2
Resync 2
channels, AC
and AD.
Write a 0,
then write a 1.
FMPU_RESY
NC4A
Resync 4
channels
A[A:D].
Write a 0,
then write a 1.
XAUI_MODE
A
Controls use
of XAUI link
state machine
vs. SERDES
link State
machine for
bank A
00
30821
A9
NOCHALGN
A
Bypass chan-
nel alignment
demuxed data
directly to
FPGA for
bank A
Reserved for future use
00
30822
30823
30830
30831
30832
30833
A10
A11
A12
A13
A14
A15
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
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ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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