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參數(shù)資料
| 型號(hào)： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 9/48頁(yè) |
| 文件大小： | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
9
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Pin Descriptions
(continued)
Table 5. Special Mode Configurations
Table 6. Clock and Chip Reset
Pin No.
42
Pin Name
PAUSE
I/O
I
Pin Description
Pause
. During reset:
Logic level of this pin is latched into register 4, bit 10
of all four ports. It is used for informing the autonego-
tiation link partner that the MAC sublayer has pause/
flow control capability of operation when set in full-
duplex mode. This must
not
be set to 1 unless FD is
also set. A weak resistive pull-up/pull-down is
required to program this function.
Open-Drain Output
. This pin has open-drain output.
Its active-low output indicates interrupt condition.
Test Mode Select
. To allow parallel access to this
register. Users should connect it to low.
1 = test mode.
0 = normal operation.
Isolate
. This is an input pin that controls MII isolate
mode. In isolate mode, all MII inputs are ignored and
MII outputs are tri-stated.
41
INTZ
I/O
158
TESTMSEL
I
44
ISOLATE
I
Pin No.
147
159
Pin Name
CLK_25
RSTZ
I/O
I
I
Pin Description
25 MHz Reference Clock Input
.
Reset
. A hardware reset is accomplished by apply-
ing a negative pulse, with a duration of at least 1 ms.
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