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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 25/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
25
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Table 12. Status Register Bit Definitions (Register 1h)
9
Restart Autonegotiation
1—Restart autonegotiation process
0—Normal operation
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation pro-
cess has commenced.
1—Full-duplex mode
0—Half-duplex mode
If autonegotiation is disabled, this bit
determines the duplex mode for the link.
At powerup or reset, this bit is set to 1 only
if ANEN pin detects a logic 0 and either
100FD or 10FD pin detects a logic 1.
1—Enable COL signal test
0—Disable COL signal test
When set, this bit will cause the COL sig-
nal of MII interface to be asserted in
response to the assertion of TXEN
Not used.
R/W, SC
0h
8
Duplex Mode
R/W
Pin
7
Collision Test (only applica-
ble while in PHY loopback
mode)
R/W
0h
6:0
Reserved
RO
0h
Bit(s)
15
Name
100Base-T4
Description
R/W
RO
Default
0h
1—Capable of 100Base-T4
0—Not capable of 100Base-T4
This bit is hardwired to 0, indicating that
the LU3X34FT does not support
100Base-T4.
1—Capable of 100Base-X full-duplex
mode
0—Not capable of 100Base-X full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FT supports 100Base-X full-
duplex mode.
1—Capable of 100Base-X half-duplex
mode
0—Not capable of 100Base-X half-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FT supports 100Base-X half-
duplex mode.
1—Capable of 10 Mbits/s full-duplex
mode
0—Not capable of 10 Mbits/s full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FT supports 10Base-T full-
duplex mode.
14
100Base-X Full Duplex
RO
1h
13
100Base-X Half Duplex
RO
1h
12
10 Mbits/s Full Duplex
RO
1h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 11. Control Register (Register 0h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| LUC4AC01 | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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