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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
21
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
(continued)
5-7911(F)
Figure 5. Hardware RESET Configurations
I/O PIN
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
10 k
10 k
V
CC
PHY Address
The PHY device address is stored in bits [4:0] of the
PHY address register (register address 19h). The
upper 3 bits of this field are initialized by the three I/O
pins designated as PHY[4:2] during powerup or hard-
ware reset and can be changed afterward by writing
into this register address (19h). The lower 2 bits are ini-
tialized to the port number of the PHY. These unique
5-bit addresses are used during serial management
interface communication.
LED Configuration
The LU3X34FT provides four LED output pins for each
of its four ports. In addition to the default functions
associated with their pin names, there are several reg-
isters that allow users to customize LED operations.
Register 11h (programmable LED register) at PHY
address 2 implement even more flexible LED configura-
tions. Via the programmable LED register, each of the
LEDs may be configured to operate in one the following
modes: link, speed, duplex, receive, transmit, solid
when link is up and blinks during activity, remote fault,
and collision. Bits [0:3] in these registers allow the user
to invert the on/off logic for each of these four program-
mable LEDs individually.
Note that all LED circuits are switched under the con-
trol of the programmable LED register whenever the
content of register 11h differs from its default value.
Register 17h implements more LED configuration fun-
citons. With these registers, unused LED can be indi-
vidually turned off to reduce power consumption.
Fiber Mode Select
A logic 1 level on pin 151, 157, 48, or 54 sets each
channel in fiber mode individually. These pins are
latched during reset operation. Pin 54 sets channel 3,
pin 48 sets channel 2, pin 157 sets channel 1, and pin
151 sets channel 0 of the quad.
Autonegotiation and Speed Configuration
The four sets of five pins listed in Table 9 configure the
speed capability of each channel of LU3X34FT. The
logic state of these pins, at powerup or reset, are
latched into the advertisement register (register
address 04h) for autonegotiation purpose. These pins
are also used for evaluating the default value in the
base mode control register (register 00h) according to
the following table.
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