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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
31
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers
(continued)
Table 20. Receive Error Counter (Register 15h)
Table 21. PHY Control/Status Register (Register 17h)
Bit(s)
15:0
Name
Description
R/W
RO,
COR
Default
0h
RX Error Count
Number of receive errors since last reset.
The counter is incremented once for each
packet that has receive error condition
detected. This counter may roll over
depending on value of the CSMODE bit
(bit 13 of register 17h).
Bit(s)
15
14
Name
Reserved
FOSEL
Description
R/W
RO
RO
Default
0h
Pin
Reserved.
1—Fiber mode
0—TX mode
For 100Base-X operation, this bit deter-
mines whether LU3X34FT interfaces with
the network through the internal
100Base-TX transceiver or using external
fiber-optic transceiver. It is initialized to the
logic level of FOSEL pin at powerup, hard-
ware, or software reset.
1—Counter sticks at FFFFh
0—Counters roll over
This bit controls the operation of false car-
rier counter, and receive error counters.
1—Tri-state transmit pairs
0—Normal operation
When this bit is set, the twisted-pair trans-
mitter outputs af all four ports are tri-
stated. Note that the twisted-pair transmit
driver can be tri-stated by either this bit or
the TPTXTR pin (pin 43).
13
CSMODE
R/W
0h
12
TPTXTR
R/W
0h
11
ThunderLAN Interrupt Enable 1—MDIO ThunderLAN interrupt enabled
0—MDIO ThunderLAN interrupt disabled
This bit enables/disables the TI Thunder-
LAN interrupt mechanism.
MF Preamble Suppression
Enable
0—MDIO preamble suppression disabled
LU3X34FT can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble sup-
pression function.
Speed Status
1—PHY is in 100 Mbits/s mode
0—PHY is in 10 Mbits/s mode
This value is not defined during the auto-
negotiation period.
R/W
0h
10
1—MDIO preamble suppression enabled
R/W
1h
9
RO
0h
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