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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大小： | 720K |
| 代理商： | LU3X34FT |
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LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
24
Lucent Technologies Inc.
14
Loopback
1—Enable loopback mode
0—Disable loopback mode
This bit controls the PHY loopback opera-
tion that isolates the network transmitter
outputs (TX±) and routes the MII transmit
data to the MII receive data path. This
function should only be used when auto-
negotiation is disabled (bit 12 = 0). The
specific PHY (10Base-T or 100Base-X)
used for this operation is determined by
bits 12 and 13 of this register.
1—100 Mbits/s
0—10 Mbits/s
Link speed is selected by this bit or by
autonegotiation if bit 12 of this register is
set (in which case, the value of this bit is
ignored). At powerup or reset, this bit will
be set unless ANEN detects a logic 1 or
both 100 FD and 100 HD pins detects
logic 0 state.
1—Enable autonegotiation process
0—Disable autonegotiation process
This bit determines whether the link speed
should be set up by the autonegotiation
process. It is set at powerup or hardware/
software reset, if the ANEN pin detects a
logic 1 input level.
1—Powerdown
0—Normal operation
Setting this bit puts the LU3X34FT into
powerdown mode. During the powerdown
mode, the MII interface are isolated and
TXEN signal is ignored. The management
interface remains active and can be used
to reset this bit in order to exit the power-
down mode.
1—Isolate PHY from MII
0—Normal operation
Setting this control bit isolates the part
from the MII, with the exception of the
serial management interface. When this
bit is asserted, the LU3X34FT does not
respond to TXD[3:0], TXEN, and TXER
inputs, and it presents a high impedance
on its TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. This bit
is initialized to the logic level of ISOLATE
pin at powerup or hard reset. Value of this
bit also follows the ISOLATE pin transition.
R/W
0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
R/W
Pin
11
Powerdown
R/W
0h
10
Isolate
R/W
Pin
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 11. Control Register (Register 0h)
(continued)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
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| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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