參數(shù)資料
型號(hào)： LU3X34FT
廠商： Lineage Power
英文描述： Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器)
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 18/48頁(yè)
文件大?。?/td> 720K
代理商： LU3X34FT
18
Lucent Technologies Inc.
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
Functional Description
(continued)
5-7910(F)
Figure 4. 10Base-T Module Data Path
TPRX±
RECEIVE
FILTER
FILTER
SMART
SQUELCH
CLOCK
RECOVERY
10BASE-T
RECEIVE
PCS
RXCLK
CRS
RXDV
RXD[3:0]
COL
10/100
TRANSMIT
DRIVER
WAVE
SHAPER
10BASE-T
TRANSMIT
PCS
TXEN
TXER
TXD[3:0]
TXCLK
TPTX±
10M PHY
LOOPBACK
PATH
Operation Modes
The LU3X34FT 10Base-T module is capable of operat-
ing in either half-duplex mode or full-duplex mode. In
half-duplex mode the LU3X34FT functions as an IEEE
802.3 compliant transceiver with fully integrated filter-
ing. The COL pin signals squelch jabber, and the CRS
is asserted during transmit and receive. In full-duplex
mode the LU3X34FT can simultaneously transmit and
receive data.
Manchester Encoder/Decoder
. Data encoding and
transmission begins when the transmit enable input
(TXEN) goes high and continues as long as the trans-
ceiver is in good link state. Transmission ends when the
transmit enable input goes low. The last transition
occurs at the center of the bit cell if the last bit is a 1, or
at the boundary of the bit cell if the last bit is 0.
Decoding is accomplished by a differential input
receiver circuit and a phase-locked loop that separates
the Manchester-encoded data stream into clock signals
and NRZ data. The decoder detects the end of a frame
when no more midbit transitions are detected. Within
one and a half bit times after the last bit, carrier sense
is deasserted.
Transmit Driver and Receiver
. LU3X34FT integrates
all the required signal conditioning functions in its
10Base-T block such that external filters are not
required. Only an isolation transformer and impedance
matching resistors are needed for the 10Base-T trans-
mit and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated properly.
Smart Squelch
. The smart squelch circuit is responsi-
ble for determining when valid data is present on the
differential receive. The LU3X34FT implements an
intelligent receive squelch on the TPRX± differential
inputs to ensure that impulse noise on the receive
inputs will not be mistaken for a valid signal. The
squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE
802.3 10Base-T standard) to determine the validity of
data on the twisted-pair inputs.
The signal at the start of the packet is checked by the
analog squelch circuit and any pulses not exceeding
the squelch level (either positive or negative, depend-
ing upon polarity) will be rejected. Once this first
squelch level is overcome correctly, the opposite
squelch level must then be exceeded within 150 ns.
Finally, the signal must exceed the original squelch
level within a further 150 ns to ensure that the input
waveform will not be rejected.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder
of the circuitry that valid data is present.
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