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參數(shù)資料
| 型號(hào)： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
28
Lucent Technologies Inc.
Table 16. Autonegotiation Link Partner Ability (Register 5h)
Table 17. Autonegotiation Expansion Register (Register 6h)
10
Flow Control
1—MAC sublayer is capable of pause-
based flow control
0—MAC sublayer not capable of pause-
based flow control
This bit advertises the MAC sublayer has
pause/flow control capability of operation
when set in full-duplex mode. This must
be set only when the PHY is advertising
10FD/100FD modes. At hardware reset,
this bit is set to 1 if the PAUSE pin detects
logic 1.
This bit defaults to 0, indicating that the
LU3X34FT does not support 100Base-
T4.
This 4-bit field contains the advertised
ability of this PHY. At powerup or reset,
the logic level of 100FD, 100HD, 10FD,
and 10HD pins are latched into bits 8
through 5, respectively.
These 5 bits are hardwired to 00001h,
indicating that the LU3X34FT supports
IEEE802.3 CSMA/CD.
R/W
Pin
9
Technology Ability Field for
100Base-T4
RO
0h
8:5
Technology Ability Field
R/W
Pin
4:0
Selector Field
R/W
01h
Bit(s)
15
Name
Next Page
Description
R/W
RO
Default
0h
1—Capable of next page function
0—Not capable of next page function
1—Link partner acknowledges reception
of the ability data word
0—Not acknowledged
1—Remote fault has been detected
0—No remote fault has been detected
Supported technologies.
Encoding definitions.
14
Acknowledge
RO
0h
13
Remote Fault
RO
0h
12:5
4:0
Technology Ability Field
Selector Field
RO
RO
0h
0h
Bit(s)
15:5
4
Name
Reserved
Description
R/W
RO
RO,
LH
Default
0h
0h
Reserved.
1—Fault has been detected
0—No fault detected
This bit is set if the parallel detection fault
state of the autonegotiation arbitration
state machine is visited during the auto-
negotiation process. It will remain set until
this register is read.
Parallel Detection Fault
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 15. Advertisement (Register 4h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| LUC4AC01 | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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