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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
23
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers
The LU3X34FT has four independant PHYs in it. Each PHY has its own identical set of registers as tabulated
below. The PHY address differentiates which PHY to be read or written into. The following tables of registers are
applicable to each register.
Table 10. MII Management Registers
Note:
Legends:
RO—Read only
R/W—Read and write capable
SC—Self-clearing
LL—Latching low, unlatch on read
LH
—
Latching high, unlatch on read
COR
—
Clear on read
Table 11. Control Register (Register 0h)
Address
0h
1h
2h—3h
4h
5h
6h
7h—Fh
11h
13h
15h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
Register Name
Basic/Extended
B
B
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Control Register
Status Register
PHY Identifier Register
Autonegotiation Advertisement Register
Autonegotiation Link Partner Ability Register
Autonegotiation Expansion Register
IEEEReserved
Programmable LED
False Carrier Counter
Receive Error Counter
PHY Control/Status Register
Config 100 Register
PHY Address Register
Config 10 Register
Status 100 Register
Status 10 Register
Interrupt Mask Register
Interrupt Status Register
Bit(s)
15
Name
Reset
Description
R/W
R/W
SC
Default
0h
1—PHY reset
0—Normal operation
Setting this bit initiates the software reset
function that resets the entire LU3X34FT
device, except for the phase-locked loop
circuit. It will relatch in autonegotiation
configuration pin values (ANEN, FOSEL,
100FD, 100HD, 10FD, 10HD) and set all
registers to their default values. The soft-
ware reset process takes 25
μ
s to com-
plete. This bit, which is self-clearing,
returns a value of 1 until the reset process
is complete.
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