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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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14
Lucent Technologies Inc.
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
Functional Description
(continued)
100Base-X Transmitter
The 100Base-X transmitter consists of functional
blocks which convert synchronous 4-bit nibble data, as
provided by the MII, to a 125 Mbits/s serial data
stream. This data stream may be routed either to the
on-chip twisted-pair PMD for 100Base-TX signaling, or
to an external fiber-optic PMD for 100Base-FX applica-
tions. The LU3X34FT implements the 100Base-X
transmit state machine as specified in the IEEE802.3u
standard, Clause 24 and comprises the following func-
tional blocks in its data path:
I
Symbol encoder
I
Scrambler block
I
Parallel/Serial converter and NRZ/NRZI encoder
block
Symbol Encoder
. The symbol encoder converts 4-bit
(4B) nibble data generated by the MAC into 5-bit (5B)
symbols for transmission. This conversion is required
to allow control symbols to be combined with data sym-
bols. Refer to the table below for 4B to 5B symbol map-
ping.
Following onset of the TXEN signal, the 4B/5B symbol
encoder replaces the first two nibbles of the preamble
from the MAC frame with a /J/K code-group pair (11000
10001) start-of-stream delimiter (SSD). The symbol
encoder then replaces subsequent 4B codes with cor-
responding 5B symbols. Following negation of the
TXEN signal, the encoder substitutes the first two IDLE
symbols with a /T/R code-group pair (01101 00111)
end-of-stream delimiter (ESD) then continuously injects
IDLE symbols into the transmit data stream until the
next transmit packet is detected.
Assertion of the TXER input while the TXEN input is
also asserted will cause the LU3X34FT to substitute
HALT code-groups for the 5B code derived from data
present at TXD[3:0]. However, the SSD (/J/K) and ESD
(/T/R) will not be substituted with HALT code-groups.
As a result, the assertion of TXER while TXEN is
asserted will result in a frame properly encapsulated
with the /J/K and /T/R delimiters which contains HALT
code-groups in place of the data code-groups.
The 100 Mbit symbol decoder translates all invalid
code-groups into 0Eh by default. In case the ACCEPT
HALT register is set (bit 5 of register 18h), the HALT
code-group (00100) is translated into 05h instead.
Table 8. Symbol Coding Table
Symbol
Name
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
5B Code
[4:0]
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
10001
01101
00111
4B Code
[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
undefined
0101
0101
undefined
undefined
Interpretation
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
IDLE: interstream fill code
First start-of-stream delimiter
Second start-of-stream delimiter
First end-of-stream delimiter
Second end-of-stream delimiter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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