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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網收發(fā)器) |
| 中文描述： | 四3伏10/100以太網收發(fā)器德克薩斯州/外匯（四3伏10/100以太網收發(fā)器） |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
11
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
The LU3X34FT integrates four 100Base-X physical
sublayer (PHY), 100Base-TX physical medium depen-
dent (PMD) transceiver, and four complete 10Base-T
modules into a single-chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. It also supports
100Base-FX operation through external fiber-optic
transceivers. This device provides an IEEE802.3u
compliant media independent interface (MII) to commu-
nicate between the physical signaling and the medium
access control (MAC) layers for both 100Base-X and
10Base-T operations. The device is capable of operat-
ing in either full-duplex mode or half-duplex mode in
either 10 Mbits/s or 100 Mbits/s operation. Operational
modes can be selected by hardware configuration pins,
software settings of management registers, or deter-
mined by the on-chip autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
I
100Base-X physical coding sublayer (PCS)
I
100Base-X physical medium attachment (PMA)
I
Twisted-pair transceiver (PMD)
The 100Base-X and 10Base-T sections share the fol-
lowing functional blocks:
I
Clock synthesizer module (CSM)
I
MII registers
I
IEEE 802.3u autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X34FT implements IEEE802.3u Clause 22
compliant MII interface as described below.
Interface Signals
Transmit Data Interfaces
. Each MII transmit data
interface comprises seven signals: TXD[3:0] are the
nibble size data path, TXEN signals the presence of
data on TXD, TXER indicates substitution of data with
the HALT symbol, and TXCLK carries the transmit
clock that synchronizes all the transmit signals. TXCLK
is supplied by the on-chip clock synthesizer.
Receive Data Interfaces
. Each receive data interface
also comprises seven signals: RXD[3:0] are the nibble
size data path, RXDV signals the presence of data on
RXD, RXER indicates the validity of data, and RXCLK
carries the receive clock. Depending upon the opera-
tion mode, RXCLK signal is generated by the clock
recovery module of either the 100Base-X or 10Base-T
receiver.
Status Interface
. Two status signals, COL and CRS,
are generated in each of the four channels to indicate
collision status and carrier sense status to the MAC.
COL is asserted asynchronously whenever the respec-
tive channel of LU3X34FT is transmitting and receiving
at the same time in a half-duplex operation mode. CRS
is asserted asynchronously whenever there is activity
on either the transmitter or the receiver. In full-duplex
mode, CRS is asserted only when there is activity on
the receiver.
Operation Modes
Each channel of the LU3X34FT supports three opera-
tion modes and an isolate mode as described below.
100 Mbits/s Mode
. For 100 Mbits/s operation, the MII
operates in nibble mode with a clock rate of 25 MHz. In
normal operation, the MII data at RXD[3:0] and
TXD[3:0] are 4 bits wide. In bypass mode (either
BYP_4B5B or BYP_ALIGN option selected), the MII
data takes the form of 5-bit code-groups. The least sig-
nificant 4 bits appear on TXD[3:0] and RXD[3:0] as
usual, and the most significant bits (TXD[4] and
RXD[4]) appear on the TXER and RXER pins, respec-
tively.
10 Mbits/s Nibble Mode
. For 10 Mbits/s nibble mode
operation, the TXCLK and RXCLK operate at 2.5 MHz.
The data paths are 4 bits wide using TXD[3:0] and
RXD[3:0] signal lines.
10 Mbits/s Serial Mode
. This mode is selected by
strapping the SERSEL pin (pin 136) to logic high level
during powerup or reset. When operating in this mode,
the LU3X34FT accepts NRZ serial data on the TXD[0]
input and provides NRZ serial data output on RXD[0]
with a clock rate of 10 MHz. The unused MII inputs and
outputs (TXD[3:1] and RXD[3:1]) are ignored during
serial mode. The PCS control signals, CRS and COL,
continue to function normally. RXDV, RXER, and TXER
signals are also ignored.
MII Isolate Mode
. The LU3X34FT implements an MII
isolate mode that is controlled by bit 10 of each one of
the four control registers (register 0h). At reset,
LU3X34FT will initialize this bit to the logic level of the
ISOLATE pin (pin 44). After reset, content of this regis-
ter follows the logic level of the ISOLATE pin. Setting
the bit to a 1 will also put the port in MII isolate mode.
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