參數(shù)資料
型號(hào)： LU3X34FT
廠商： Lineage Power
英文描述： Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器)
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 20/48頁(yè)
文件大小： 720K
代理商： LU3X34FT
20
Lucent Technologies Inc.
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
Functional Description
(continued)
When autonegotiation is enabled, the LU3X34FT trans-
mits the abilities programmed into the autonegotiation
advertisement register at address 04h via FLP bursts.
Any combination of 10 Mbits/s, 100 Mbits/s, half-
duplex, and full-duplex modes may be selected. Auto-
negotiation controls the exchange of configuration
information. Upon successful autonegotiation, the abili-
ties reported by the link partner are stored in the auto-
negotiation link partner ability register at address 05h.
The contents of the autonegotiation link partner ability
register are used to automatically configure to the high-
est performance protocol between the local and far-end
nodes. Software can determine which mode has been
configured by autonegotiation by comparing the con-
tents of register 04h and 05h and then selecting the
technology whose bit is set in both registers of highest
priority relative to the following list.
1. 100Base-TX full duplex (highest priority)
2. 100Base-TX half duplex
3. 10Base-T full duplex
4. 10Base-T half duplex (lowest priority)
The basic mode control register at address 00h pro-
vides control of enabling, disabling, and restarting of
the autonegotiation function. When autonegotiation is
disabled, the speed selection bit (bit 13) controls
switching between 10 Mbits/s or 100 Mbits/s operation,
while the duplex mode bit (bit 8) controls switching
between full-duplex operation and half-duplex opera-
tion. The speed selection and duplex mode bits have
no effect on the mode of operation when the autonego-
tiation enable bit (bit 12) is set.
The basic mode status register at address 01h indi-
cates the set of available abilities for technology types
(bits 15 to 11), autonegotiation ability (bit 3), and
extended register capability (bit 0). These bits are hard-
wired to indicate the full functionality of the LU3X34FT.
The BMSR also provides status on the following:
1. Whether autonegotiation is complete (bit 5).
2. Whether the link partner is advertising that a remote
fault has occurred (bit 4).
3. Whether a valid link has been established (bit 2).
The autonegotiation advertisement register at address
04h indicates the autonegotiation abilities to be adver-
tised by the LU3X34FT. All available abilities are trans-
mitted by default, but any ability can be suppressed by
writing to this register or configuring external pins.
The autonegotiation link partner ability register at
address 5h indicates the abilities of the link partner as
indicated by autonegotiation communication. The con-
tents of this register are considered valid when the
autonegotiation complete bit (bit 5, register address
01h) is set.
Reset Operation
The LU3X34FT can be reset either by hardware or soft-
ware. A hardware reset is accomplished by applying a
negative pulse, with a duration of at least 1 ms, to the
RSTZ pin of the LU3X34FT during normal operation. A
software reset is activated by setting the RESET bit in
the basic mode control register (bit 15, register 00h).
This bit is self-clearing and, when set, will return a
value of 1 until the software reset operation has com-
pleted.
Hardware reset operation samples the pins and initial-
izes all registers to their default values. This process
includes re-evaluation of all hardware configurable reg-
isters. A hardware reset affects all four PHYs in the
device.
A software reset can reset an individual PHY. It latches
all configuration pins dedicated to the corresponding
PHY but does not latch the external pins common to all
four PHYs.
Logic levels on several I/O pins are detected during the
hardware and software reset period to determine the
initial functionality of LU3X34FT. Some of these pins
are used as output ports after reset operation.
Care must be taken to ensure that the configuration
setup will not interfere with normal operation. Dedi-
cated configuration pins can be tied to Vcc or ground
directly. Configuration pins multiplexed with logic level
output functions should be either weakly pulled-up or
weakly pulled-down through resistors. Configuration
pins multiplexed with LED outputs should be set up
with one of the following circuits shown in Figure 5.
相關(guān)PDF資料
PDF描述
LU3X51FT-J80 Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器)
LU3X54FTL Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器)
LU5X31F Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器)
LUC4AB01 ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM))
LUC4AC01 ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LU3X34FTR 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX
LU3X34FTR-HS128-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX
LU3X54FT 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
LU3X54FTL 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX
LU3X54FTLHS208 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*