- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384634 > LU3X34FT (Lineage Power) Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
16
Lucent Technologies Inc.
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
Functional Description
(continued)
Clock Recovery
. The clock recovery module accepts
125 Mbits/s scrambled NRZI data stream from either
the on-chip 100Base-TX receiver or from an external
100Base-FX transceiver. The LU3X34FT uses an
onboard digital phase-locked loop (PLL) to extract clock
information of the incoming NRZI data, which is then
used to retime the data stream and set data bound-
aries.
After power-on or reset, the PLL locks to a free-running
25 MHz clock derived from the external clock source.
When initial lock is achieved, the PLL switches to lock
to the data stream, extracts a 125 MHz clock from the
data and use it for bit framing of the recovered data.
NRZI/NRZ and Serial/Parallel Conversion
The recovered data is converted from NRZI to NRZ.
The data is not necessarily aligned to 4B/5B code-
group’s boundary.
Data Descrambling
. The descrambler acquires syn-
chronization with the data stream by recognizing IDLE
bursts of 40 or more bits and locking its deciphering lin-
ear feedback shift register (LFSR) to the state of the
scrambling LFSR. Upon achieving synchronization, the
incoming data is XORed by the deciphering LFSR and
descrambled.
In order to maintain synchronization, the descrambler
continuously monitors the validity of the unscrambled
data that it generates. To ensure this, a link state moni-
tor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the
descrambler, the hold timer starts a 722
μ
s countdown.
Upon detection of sufficient IDLE symbols within the
722
μ
s period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue
indefinitely given a properly operating network connec-
tion with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled IDLE sym-
bols within the 722
μ
s period, the descrambler will be
forced out of the current state of synchronization and
reset in order to re-acquire synchronization. Register
18h, bit 3, can be used to extend the timer to 2 ms.
Symbol Alignment
. The symbol alignment circuit in
the LU3X34FT determines code word alignment by
recognizing the /J/K delimiter pair. This circuit operates
on unaligned data from the descrambler. Once the /J/K
symbol pair (11000 10001) is detected, subsequent
data is aligned on a fixed boundary.
Symbol Decoding
. The symbol decoder functions as
a look-up table that translates incoming 5B symbols
into 4B nibbles. The symbol decoder first detects the
/J/K symbol pair preceded by IDLE symbols and
replaces the symbol with MAC preamble. All subse-
quent 5B symbols are converted to the corresponding
4B nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the /T/R sym-
bol pair denoting the end-of-stream delimiter (ESD).
The translated data is presented on the RXD[3:0] sig-
nal lines with RXD[0] represents the least significant bit
of the translated nibble.
Valid Data Signal
. The data valid signal (RXDV) indi-
cates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to
RXCLK. RXDV is asserted when the first nibble of
translated /J/K is ready for transfer over the media inde-
pendent interface (MII). It remains active until either the
/T/R delimiter is recognized, link test indicates failure,
or no signal is detected. On any of these conditions,
RXDV is deasserted.
Receiver Errors
. The RXER signal is used to commu-
nicate receiver error conditions. While the receiver is in
a state of holding RXDV asserted, the RXER will be
asserted for each code word that does not map to a
valid code-group.
100Base-X Link Monitor
The 100Base-X link monitor function allows the
receiver to ensure that reliable data is being received.
Without reliable data reception, the link monitor will
HALT both transmit and receive operations until such
time that a valid link is detected.
The LU3X34FT performs the link integrity test as out-
lined in IEEE 100Base-X (Clause 24) link monitor state
diagram. The link status is multiplexed with 10 Mbits/s
link status to form the reportable link status bit in serial
management register 1, and driven to the LEDLNK
pins.
When persistent signal energy is detected on the net-
work, the logic moves into a link-ready state after
approximately 500
μ
s, and waits for an enable from the
autonegotiation module. When received, the link-up
state is entered, and the transmit and receive logic
blocks become active. Should autonegotiation be dis-
abled, the link integrity logic moves immediately to the
link-up state after entering the link-ready state.
Carrier Sense
. Carrier sense (CRS) for 100 Mbits/s
operation is asserted upon the detection of two non-
contiguous zeros occurring within any 10-bit boundary
of the receive data stream.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| LUC4AC01 | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。