參數(shù)資料
型號(hào): LU3X34FT
廠商: Lineage Power
英文描述: Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器)
中文描述: 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯(四3伏10/100以太網(wǎng)收發(fā)器)
文件頁數(shù): 15/48頁
文件大小: 720K
代理商: LU3X34FT
Lucent Technologies Inc.
15
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
H
V
V
V
V
V
V
V
V
V
V
00100
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
HALT: transfer error
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Symbol
Name
5B Code
[4:0]
4B Code
[3:0]
Interpretation
Scrambler Block
. For 100Base-TX applications, the
scrambler is required to control the radiated emissions
at the media connector and on the twisted-pair cable.
The LU3X34FT implements a data scrambler as
defined by the TP-PMD stream cipher function. The
scrambler uses an 11-bit ciphering linear feedback shift
register (LFSR) with the following recursive linear func-
tion:
X[n] = X[n – 11] + X[n – 9] (modulo 2)
The output of the LFSR is combined with data from the
encoder via an exclusive-OR logic function. By scram-
bling the data, the total energy launched onto the cable
is randomly distributed over a wide frequency range.
A seed value for the scrambler function can be loaded
by setting bit 4 of register 18h. When this bit is set, the
content of bits 10 through 0 of register 19h that com-
pose the 5-bit PHY address and a 6-bit user seed, will
be loaded into the LFSR. By specifying unique seed
value for each PHY in a system, the total EMI energy
produced by a repeater type application can be
reduced.
Parallel to Serial and NRZ-NRZI Conversion
. After
the transmit data stream is scrambled, data is loaded
into a shift register and clocked out with a 125 MHz
clock into a serial bit stream. The serialized data is fur-
ther converted from NRZ to NRZI format, which pro-
duces a transition on every Logic 1 and no transition on
Logic 0.
Collision Detect
. During 100 Mbits/s half-duplex oper-
ation, collision condition is detected if the transmitter
and receiver become active simultaneously. Collision
detection is indicated by the COL pin of the MII. For
full-duplex applications, the COL signal is never
asserted. A collision test register exists at address 0,
bit 7. When this bit is high, COL is asserted if TXEN is
high.
100Base-X Receiver
The 100Base-X receiver consists of functional blocks
required to recover and condition the 125 Mbits/s
receive data stream. The LU3X34FT implements the
100Base-X receive state machine diagram as given in
ANSI/IEEEStandard 802.3u, Clause 24. The
125 Mbits/s receive data stream may originate from the
on-chip twisted-pair transceiver in a 100Base-TX appli-
cation. Alternatively, the receive data stream may be
generated by an external optical receiver as in a
100Base-FX application.
The receiver block consists of the following functional
blocks:
I
Clock recovery module
I
NRZI/NRZ and serial/parallel decoder
I
Descrambler
I
Symbol alignment block
I
Symbol decoder
I
Collision detect block
I
Carrier sense block
I
Stream decoder block
Functional Description
(continued)
Table 8. Symbol Coding Table
(continued)
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