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參數(shù)資料
| 型號(hào)： | LU3X34FT |
| 廠(chǎng)商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 7/48頁(yè) |
| 文件大小： | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
7
Advance Data Sheet
June 1999
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
142, 143,
144, 145
115, 116,
117, 118
86, 85, 84, 83
59, 58, 57, 56
141, 112, 87,
60
127, 128,
129, 133
103, 104,
105, 108
96, 93, 92, 91
76, 75, 74, 73
102, 97, 77,
126
62
TXD_0[3:0]
I
MII Transmit Data for Port 0
.
TXD_1[3:0]
I
MII Transmit Data for Port 1
.
TXD_2[3:0]
TXD_3[3:0]
TXER_[0:3]
I
I
I
MII Transmit Data for Port 2
.
MII Transmit Data for Port 3
.
Transmit Error Signal for Each Port
.
RXD_0[3:0]
O
MII Receive Data for Port 0
.
RXD_1[3:0]
O
MII Receive Data for Port 1
.
RXD_2[3:0]
RXD_3[3:0]
RXER_[0:3]
O
O
O
MII Receive Data for Port 2
.
MII Receive Data for Port 3 in Switch Mode
.
Receive Error Condition for Ports 0—3
.
CRS_3/
PHY_AD[4]
I/O
PHY Address 4
. During reset, this pin is input pin for
PHY_ADDRESS[4] configuration. This pin has an
internal 40 k
pull-down.
CRS Output
. After reset, this is the CRS output for
port 3. It is asserted only during receive activity.
PHY Address 3
. During reset, this is an input pin for
PHY_ADDRESS[3] configuration. This pin has an
internal 40 k
pull-down.
88
CRS_2/
PHY_AD[3]
I/O
CRS Output
. After reset, this is the CRS output for
port 2. It is asserted only during receive activity.
PHY Address 2
. During reset, this is an input pin for
PHY_ADDRESS[2] configuration. This pin has an
internal 40 k
pull-down.
111
CRS_1/
PHY_AD[2]
I/O
CRS Output
. After reset, this is the CRS output for
port 1. It is asserted only during receive activity.
Serial Select
. During reset, this is an input pin,
serial select for 10 Mbits/s mode. This pin has an
internal 40 k
pull-down.
136
CRS_0/
SERSEL
I/O
CRS Output
. After reset, this is the CRS output for
port 0. It is asserted only during receive activity.
Receive Data Valid Signal for Ports 0—3
.
134, 109, 90,
72
125, 101, 98,
78
RXDV_[0:3]
O
RXCLK_[0:3]
O
Receive Clock Output for Ports 0—3
. Its frequency
is 25 MHz in 100 Mbit mode, 2.5 MHz in 10 Mbit nib-
ble mode, and 10 MHz in 10 Mbit serial mode.
Management Data Port
. An external resistive pull-
up is needed on this pin.
Management Clock
. Max clock rate is 2.5 MHz.
64
MDIO
I/O
63
MDC
I
Pin No.
Pin Name
I/O
Pin Description
Pin Descriptions
(continued)
Table 3. MII Interface
(continued)
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X34FTR | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
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| LU3X54FT | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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