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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 720K |
| 代理商： | LU3X34FT |
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Lucent Technologies Inc.
LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
Functional Description
(continued)
When in isolate mode, the specified port on the
LU3X34FT does not respond to packet data present at
TXD[3:0], TXEN, and TXER inputs and presents a high
impedance on the TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. The LU3X34FT will
continue to respond to all management transactions
while the PHY is in isolate mode.
Serial Management Interface
The serial management interface (SMI) is used to both
obtain status from and to configure the PHY. This
mechanism corresponds to the MII specifications for
100Base-X (Clause 22), and supports registers 0
through 6. Additional vendor-specific registers are
implemented within the range of 16 to 31. All the regis-
ters are described in the register section.
Management Register Access
. The SMI consists of
two pins, management data clock (MDC) and manage-
ment data input/output (MDIO). The LU3X34FT is
designed to support an MDC frequency ranging up to
the IEEEspecification of 2.5 MHz. The MDIO line is bi-
directional and may be shared by up to 32 devices.
The MDIO pin requires a pull-up resistor which, during
IDLE and turnaround periods, will pull MDIO to a logic
one state. Each MII management data frame is 64 bits
long. The first 32 bits are preamble consisting of 32
contiguous logic one bits on MDIO and 32 correspond-
ing cycles on MDC. Following preamble is the start-of-
frame field indicated by a <01> pattern. The next field
signals the operation code (OP): <10> indicates READ
from MII management register operation, and <01>
indicates WRITE to MII management register opera-
tion. The next two fields are PHY device address and
MII management register address. Both of them are
5 bits wide and the most significant bit is transferred
first.
During READ operation, a 2-bit turnaround (TA) time
spacing between register address field and data field is
provided for the MDIO to avoid contention. Following
the turnaround time, a 16-bit data stream is read from
or written into the MII management registers of the
LU3X34FT.
The LU3X34FT supports a preamble suppression
mode as indicated by a 1 in bit 6 of the basic mode sta-
tus register (BMSR, address 01h). If the station man-
agement entity (i.e., MAC or other management
controller) determines that all PHYs in the system sup-
port preamble suppression by reading a 1 in this bit,
then the station management entity need not generate
preamble for each management transaction. The
LU3X34FT requires a single initialization sequence of
32 bits of preamble following powerup/hardware reset.
This requirement is generally met by the mandatory
pull-up resistor on MDIO or the management access
made to determine whether preamble suppression is
supported. While the LU3X34FT will respond to man-
agement accesses without preamble, a minimum of
one idle bit between management transactions is
required as specified in IEEE802.3u.
The PHY device address for LU3X34FT is stored in the
PHY address register (register address 19h). Upper 3
bits of the PHY address are initialized by the three I/O
pins designated as PHY_AD[4:2] during powerup or
hardware reset and can be changed afterward by writ-
ing into register address 19h. The lower 2 bits of the
PHY address are initialized to the port number of the
PHY during powerup or hardware reset.
MDIO Interrupt
. The LU3X34FT implements interrupt
capability that can be used to notify the management
station of certain events. Interrupt requested by any of
the four PHYs is combined in this pin. It generates an
active-low interrupt on the INTZ output pin whenever
one of the interrupt status registers (register address
1Eh) becomes set while its corresponding interrupt
mask register (register address 1Dh) is unmasked.
Reading the interrupt status register (register 1Eh)
shows the source of the interrupt and clears the inter-
rupt output signal.
In addition to the INTZ pin, the LU3X34FT can also
support the interrupt scheme used by the TI Thunder-
LAN MAC. This option can be enabled by setting bit 11
of register 17h. Whenever this bit is set, the interrupt is
signaled through the INTZ pin and embedded in the
MDIO signal.
100Base-X Module
The LU3X34FT implements 100Base-X compliant PCS
and PMA and 100Base-TX compliant TP-PMD as illus-
trated in Figure 3. Bypass options for each of the major
functional blocks within the 100Base-X PCS provides
flexibility for various applications. 100 Mbits/s PHY
loopback is included for diagnostic purposes.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
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| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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