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參數(shù)資料
| 型號： | LU3X34FT |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（四3伏10/100以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 6/48頁 |
| 文件大小： | 720K |
| 代理商： | LU3X34FT |
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LU3X34FT
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Advance Data Sheet
June 1999
6
Lucent Technologies Inc.
Pin Descriptions
Table 1. Twisted-Pair Magnetic Interface
Table 2. Twisted-Pair Transceiver Control/Transmitter Control
Table 3. MII Interface
Pin No.
7, 12, 29, 34
8, 11, 30, 33
Pin Name
TX+_[0:3]
TX–_[0:3]
I/O
O
Pin Description
Transmit Driver Pairs
. These pins are used to send
100Base-T MLT-3 signals across category 5 UTP
10Base-T Manchester signals across category 3/5
UTP cable in twisted-pair operation, or PECL data in
fiber mode.
Receive Pair
. These pins receive 100Base-T MLT-3
data, 10Base-T Manchester data from the UTP
cable in twisted-pair mode, or PECL data in fiber
mode.
3, 16, 25, 38
4, 15, 26, 37
RX+_[0:3]
RX–_[0:3]
I
Pin No.
6, 13, 28, 35
Pin Name
REF100[0:3]
I/O
I
Pin Description
Reference Pin for 100 Mbits/s Twisted-Pair Driver
.
The value of the connected resistor is
TBD
.
Reference Pin for 10 Mbits/s Twisted-Pair Driver
.
The value for the connected resistor is
TBD
.
Transmit Driver Edge Rate Control
. When set to 1,
the rise time of the transmit data will be less than
TBD
ns. This pin is latched at powerup and reset.
Network Interface Tri-State Control
. When high,
the transmit drivers for all four ports are tri-stated.
23
REF10
I
160
ER
I
43
TPTXTR
I
Pin No.
1, 122, 121,
40
Pin Name
10FD[0:3]
I/O
I
Pin Description
10 Mbits/s Full-duplex Capability Configuration
Input
. It is latched into bit 6 of register 04h (autone-
gotiation ability register) at reset. It is also used to
configure a port to 10 Mbits/s full-duplex mode if
autonegotiation is disabled. Each of these pins has
an internal 40 k
pull-up.
100 Mbits/s Full-duplex Capability Configuration
Input
. During reset, it is latched into bit 8 of register
04h (autonegotiation ability register) at reset. It is
also used to configure a port to 100 Mbits/s full-
duplex mode if autonegotiation is disabled. Each of
these pins has an internal 40 k
pull-up.
After reset:
In half-duplex mode, these pins are an output indi-
cating collision status.
MII Transmit Clock For Ports 0 Through 2
. Its fre-
quency is 2.5 MHz in 100 Mbit mode, 25 MHz in
10 Mbit nibble mode, and 10 MHz in 10 Mbit serial
mode.
Transmit Enable
. Ports 0 through 3.
135, 110, 89,
61
COL_[0:3]/
100FD_[0:3]
I/O
138, 120, 81,
70
TXCLK_[0:3]
O
146, 119, 82,
55
TXEN_[0:3]
I
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