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參數資料
| 型號： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數： | 8/62頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | H5MS5162DFR-K3M |
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Rev 1.3 / Apr. 2009
16
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank.
DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and Truth Table3,
and according to Truth Table 4.
Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the
''row active'' state.
Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
to each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met.
Once tRFC is met, the LP DDR will be in an
''all banks idle'' state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the LP DDR will be in an
''all banks idle'' state.
Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end
the READ prior to asserting a WRITE command.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
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