參數(shù)資料
型號： H5MS5162DFR-K3M
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù)： 18/62頁
文件大?。?/td> 1314K
代理商： H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
25
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 2 of 2)
Parameter
Symbol
DDR400
DDR370
DDR333
DDR266
DDR200
Unit Note
Min Max Min Max Min Max Min Max Min Max
MODE REGISTER SET Command
Period
tMRD
2
-
2
-
2
-
2
-
2
-
tCK
MRS(SRR) to Read Command Period
tSRR
2
-
2
-
2
-
2
-
2
-
tCK
Minimum Time between Status Regis-
ter Read to Next Valid Command
tSRC
CL+1
-
CL+1
-
CL+1
-
CL+1
-
CL+1
-
tCK
Write Preamble Setup Time
tWPRES
0
-
0
-
0
-
0
-
0
-
ns
12
Write Postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
13
Write Preamble
tWPRE
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
tCK
Read Preamble
CL = 3
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
14
CL = 2
tRPRE
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.1
tCK
14
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE to PRECHARGE Command
Period
tRAS
40
70,0
00
42
70,0
00
42
70,0
00
45
70,0
00
50
70,0
00
ns
ACTIVE to ACTIVE Command Period
tRC
55
-
58.2
-
60
-
75
-
80
-
ns
AUTO REFRESH to ACTIVE/AUTO
REFRESH Command Period
tRFC
72
-
72
-
72
-
72
-
72
-
ns
ACTIVE to READ or WRITE Delay
tRCD
15
-
16.2
-
18
-
22.5
-
30
-
ns
15
PRECHARGE Command Period
tRP
15
-
16.2
-
18
-
22.5
-
30
-
ns
15
ACTIVE Bank
A to ACTIVE Bank B
Delay
tRRD
10
-
10.8
-
12
-
15
-
15
-
ns
WRITE Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Auto Precharge Write Recovery
+ Precharge Time
tDAL
(tWR/tCK) + (tRP/tCK)
16
Internal Write to Read Command
Delay
tWTR
1
-
1
-
1
-
1
-
1
-
tCK
Self Refresh Exit to next valid
Command Delay
tXSR
120
-
120
-
120
-
120
-
120
-
ns
Exit Power Down to next valid
Command Delay
tXP
tIS +
2CLK
-
tIS +
1CLK
-
tIS +
1CLK
-
tIS +
1CLK
-
tIS +
1CLK
-
ns
CKE
min. Pulse Width(High and Low)
tCKE
1
-
1
-
1
-
1
-
1
-
tCK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
17
Refresh Period
tREF
-
64
-
64
-
64
-
64
-
64
ms
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
H5MS5162DFR-L3M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM
H5MS5162EFR 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM)
H5MS5162EFR-J3M 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes
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