參數(shù)資料
型號: H5MS5162DFR-K3M
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù): 16/62頁
文件大?。?/td> 1314K
代理商: H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
23
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is 1V/ns
3. Definitions for IDD:
LOW is defined as VIN 0.1 * VDDQ
HIGH is defined as VIN 0.9 * VDDQ
STABLE is defined as inputs stable at a HIGH or LOW level
SWITCHING is defined as
- address and command: inputs changing between HIGH and LOW once per two clock cycles
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle
DM and DQS are STABLE
4. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional
function.
5. IDD values are for full operating range of voltage and temperature.
VDD, VDDQ = 1.7V ~ 1.95V. Temperature = -30oC ~ +85oC
DC CHARACTERISTICS - IDD6
Note:
1. Related numerical values in this 45oC are examples for reference sample value only.
2. With a on-chip temperature sensor, auto temperature compensated self refresh will automatically adjust the interval of self-refresh
operation according to case temperature variations.
Temp.
(oC)
Memory Array
Unit
4 Banks
2 Banks
1 Bank
45
250
220
200
uA
85
500
400
300
uA
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