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參數(shù)資料
| 型號(hào)： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數(shù)： | 5/62頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | H5MS5162DFR-K3M |
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Rev 1.3 / Apr. 2009
13
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
COMMAND TRUTH TABLE
DM TRUTH TABLE
Note:
1. All states and sequences not shown are illegal or reserved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge
4. Burst Terminate applies to only Read bursts with auto precharge disabled. This command is undefined and should not be used for
Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are
don
't care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
8. All address inputs and I/O are
''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select among MRS, EMRS and SRR.
11. Used to mask write data, provided coincident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Function
CS
RAS
CAS
WE
BA
A10/AP ADDR Note
DESELECT (NOP)
H
X
2
NO OPERATION (NOP)
L
H
X
2
ACTIVE (Select Bank and activate Row)
L
H
V
Row
READ (Select bank and column and start read burst)
L
H
L
H
V
L
Col
READ with AP (Read Burst with Autoprecharge)
L
H
L
H
V
H
Col
3
WRITE (Select bank and column and start write
burst)
L
H
L
V
L
Col
WRITE with AP (Write Burst with Autoprecharge)
L
H
L
V
H
Col
3
BURST TERMINATE or enter DEEP POWER DOWN
L
H
L
X
4, 5
PRECHARGE (Deactivate Row in selected bank)
L
H
L
V
L
X
6
PRECHARGE ALL (Deactivate rows in all Banks)
L
H
L
X
H
X
6
AUTO REFRESH or enter SELF REFRESH
L
H
X
7,8,9
MODE REGISTER SET
L
V
Op code
10
Function
DM
DQ
Note
Write Enable
L
Valid
11
Write Inhibit
H
X
11
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
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