參數(shù)資料
型號(hào): H5MS5162DFR-K3M
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁(yè)數(shù): 52/62頁(yè)
文件大?。?/td> 1314K
代理商: H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
56
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Mobile DDR SDRAM Deep Power Down Entry and Exit
Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon
entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state.
Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization
routine is required following steps 4 through 11 as defined in POWER-UP and INITIALIZATION SEQUENCES.
Mobile DDR SDRAM Deep Power-Down Entry and Exit
Note:
1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering Deep Power Down mode.
3. 200us is required before any command can be applied upon exiting DPD.
4. DPD = Deep Power Down command.
5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load
mode register sequence.
DON'T CARE
NOP
DPD4
NOP
VALID5
VALID
T
0
T
1
Ta01
Ta1
Tb1
tCK
tIH
tIS
tCH
tCL
tIS
tIH
tIS
tIH
tIS
tRP2
Deep Power Down Mode
Exit Deep Power Down Mode
T=200us3
CK
CKE
COM
ADD
DQS
DQ
DM
tIS
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