- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223868 > H5MS5162DFR-K3M (HYNIX SEMICONDUCTOR INC) 32M X 16 DDR DRAM, 0.5 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數(shù)： | 6/62頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | H5MS5162DFR-K3M |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Rev 1.3 / Apr. 2009
14
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
CKE TRUTH TABLE
Note:
1. CKEn is the logic state of CKE at clock edge
n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of LP DDR immediately prior to clock edge
n.
3. COMMAND
n is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description.
9. The clock must toggle at least one time during the tXP period.
10. The clock must toggle at least once during the tXSR time.
CKEn-1
CKEn
Current State
COMMAND
n
ACTION
n
Note
L
Power Down
X
Maintain Power Down
L
Self Refresh
X
Maintain Self Refresh
L
Deep Power Down
X
Maintain Deep Power
Down
L
H
Power Down
NOP or DESELECT
Exit Power Down
5,6,9
L
H
Self Refresh
NOP or DESELECT
Exit Self Refresh
5,7,10
L
H
Deep Power Down
NOP or DESELECT
Exit Deep Power Down
5,8
H
L
All Banks Idle
NOP or DESELECT
Precharge Power
Down Entry
5
H
L
Bank(s) Active
NOP or DESELECT
Active Power Down
Entry
5
H
L
All Banks Idle
AUTO REFRESH
Self Refresh entry
H
L
All Banks Idle
BURST TERMINATE
Enter Deep Power
Down
H
See the other Truth Tables
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| H6101NL | DATACOM TRANSFORMER FOR GENERAL PURPOSE APPLICATION(S) |
| H6E1PC03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E1PX03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, PLUG |
| H6E2PC03130001 | MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E2PX03130001 | MULTIWAY RACK AND PANEL CONN, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。