參數(shù)資料
型號(hào)： H5MS5162DFR-K3M
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁(yè)數(shù)： 54/62頁(yè)
文件大?。?/td> 1314K
代理商： H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
58
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Clock Stop Mode
Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption
during idle periods of the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
● The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of required clock pulses per access
command depends on the device's AC timing parameters and the clock frequency;
● The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;
● CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be
entered with CK held LOW and CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command
have to be issued for at least one clock cycle before the next access command may be applied. Additional clock pulses
might be required depending on the system characteristics.
Figure1 illustrates the clock stop mode:
● Initially the device is in clock stop mode;
● The clock is restarted with the rising edge of T0 and a NOP on the command inputs;
● With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock
stop as soon as this access command has completed;
● Tn is the last clock pulse required by the access command latched with T1.
● The timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse
required by this command and the clock is then stopped.
Clock Stop Mode
CK
ADD
CMD
NOP
Valid
Clock
Stopped
Exit Clock
Stop Mode
Valid
Command
Enter Clock
Stop Mode
Don't Care
(High-Z)
CK
CM
D
T
0
T
1
T
2
T
n
CKE
DQ,
DQS
Timing Condition
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
H5MS5162DFR-L3M 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM
H5MS5162EFR 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM)
H5MS5162EFR-J3M 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes
H5MS5162FFR-E3M 制造商:SK Hynix Inc 功能描述:
H5N1503P 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching
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