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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 9/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
9 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
pins LCKP and LCKN
D
-
1.2
-
pF
Digital inputs/outputs (pins MDSN, MDSP)
V
o(dif)(p-p)
peak-to-peak
differential
output voltage
C
o(L)
output load
capacitance
C
i
input
capacitance
R
i
input resistance
V
i
input voltage
V
idth
input differential
threshold
voltage
Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N)
V
IL
LOW-level input
voltage
V
IH
HIGH-level
input voltage
V
OL
LOW-level
output voltage
V
OH
HIGH-level
output voltage
I
IL
LOW-level input
current
I
IH
HIGH-level
input current
C
i
input
capacitance
Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)
I
O(fs)
full-scale output
current
GAIN registers
(see
Table 32
)
default value
V
O
output voltage
compliance range
V
O(cm)
common-mode
output voltage
2 V (p-p) DAC output
R
o
output
resistance
C
o
output
capacitance
OUTBN and pins OUTBN
and OUTBP
C
-
500
-
mV
between GND and pin
MDSN or MDSP
between GND and pin
MDSN or MDSP
D
-
-
<tbd>
pF
D
-
0.6
-
pF
D
C
C
-
<tbd>
<tbd>
100
-
-
-
<tbd>
<tbd>
mV
mV
V
gpd
< 50 mV
[3]
V
gpd
< 50 mV
[3]
C
GND
-
0.3V
DDD(1V8)
V
C
0.7V
DDD(1V8)
-
V
DDD(1V8)
V
pins SDO and SDIO
C
GND
-
0.1V
DDD(1V8)
V
pins SDO and SDIO
C
0.9V
DDD(1V8)
-
V
DDD(1V8)
V
maximum VIL
I
10
-
+10
A
maximum VIL
I
10
-
+10
A
D
-
1
-
pF
controlled by the analog
D
8.1
-
34
mA
D
D
D
-
2.3
-
-
-
20
-
3
2.8
250
-
V
DDA(3V3)
-
-
-
mA
V
V
V
k
1 V (p-p) DAC output
D
between pins OUTAN and
D
-
5
-
pF
Table 5.
V
DDA(1V8)
= 1.8 V; V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
C; R
L
= 50
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in
Figure 22
; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
[1]
Characteristics
…continued
Min
Typ
Max
Unit
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