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參數(shù)資料
| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 2/66頁 |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
2 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communications: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Embedded Numerically Controlled
Oscillator (NCO) with 40-bit
programmable frequency
High resolution internal digital gain and
offset control to support high
performance IQ-modulator image
rejection
Internal phase correction
Embedded complex(I/Q) digital IF
modulator
1.8 V and 3.3 V power supplies
LVDS DDR compatible input interface
with on-chip 100
terminations
LVDS DDR input clock up to 312.5 MHz
On-chip 1.25 V reference
LVDS or LVPECL compatible DAC clock
Industrial temperature range
40
C to
Inverse (sin x) / x function
Power-down mode and Sleep mode;
5-bit NCO low power mode
+85
C
72 pins small form factor HVQFN
package
Interleaved or folded I and Q data input
mode
Table 1.
Type number
Ordering information
Package
Name
HVQFN72
Description
plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10
10
0.85 mm
Version
SOT813-3
DAC1617D1G0HN
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| DAC1617D1G0HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Bulk |
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